公开(公告)号：US20160372202A1

公开(公告)日：2016-12-22

申请号：US14742054

申请日：2015-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.

Abstract translation: 本文中设想的方法和装置用于增强非易失性存储器件的程序性能。 在示例实施例中，非易失性存储器件包括包括多个层的非易失性存储器单元的3D阵列，每个层包括非易失性存储器单元的NAND串，耦合到位线的NAND串和多个SSL和字线， 所述SSL和所述字线与所述NAND串正交排列，所述字线在所述多个NAND串的表面和所述字线之间的交叉点处建立所述非易失性存储单元，所述NAND串中的每一个还包括多个SSL晶体管 将SSL耦合到NAND串，其中至少第一SSL被配置为接收第一电压，第二SSL被配置为在第二电压下接收，并且其中第二SSL更靠近字线。

公开(公告)号：US20170025179A1

公开(公告)日：2017-01-26

申请号：US14808745

申请日：2015-07-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/24 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10

Abstract: Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled to a bit line and word lines, the word lines arranged orthogonally to the NAND strings and establishing the memory cells at cross-points between surfaces of the NAND strings and the word lines, and a first set of discharge transistors positioned at an edge of the 3D array, coupled to a corresponding bit line, and configured for BL discharge, and a second set of discharge transistors positioned such that a first portion of BL potential is discharged through the first set of discharge transistors and a second portion through the second set.

Abstract translation: 本文中设想的方法和装置用于减少非易失性存储器件的位线恢复时间。 在示例性实施例中，非易失性存储器件包括非易失性存储器单元的3D阵列，包括多个块，每个块包括多个NAND串，每个NAND串耦合到位线和字线， 与NAND串正交排列的字线和在NAND串和字线的表面之间的交叉点建立存储单元，以及位于3D阵列边缘的第一组放电晶体管，耦合到相应的位线 并且被配置为用于BL放电，以及第二组放电晶体管，其定位成使得BL电位的第一部分通过第一组放电晶体管放电，并且通过第二组放电第二部分。

公开(公告)号：US10460797B2

公开(公告)日：2019-10-29

申请号：US15698812

申请日：2017-09-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Ta-Wei Lin ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Wen-Jer Tsai

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

公开(公告)号：US20170098478A1

公开(公告)日：2017-04-06

申请号：US14873486

申请日：2015-10-02

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Lee ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: G11C29/38 ,  G11C16/26 ,  G11C29/44 ,  G11C16/14

CPC classification number: G11C29/38 ,  G11C16/08 ,  G11C16/26 ,  G11C29/025 ,  G11C29/44 ,  G11C2029/1202

Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.

公开(公告)号：US09548121B2

公开(公告)日：2017-01-17

申请号：US14742944

申请日：2015-06-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Lee ,  Shaw-Hung Ku ,  Cheng-Hsien Cheng

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/115 ,  H01L21/768

CPC classification number: G11C16/0483 ,  G11C2216/02 ,  H01L21/76802 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.

Abstract translation: 本文中设想的方法和装置用于增强非易失性存储器件的效率。 在示例实施例中，非易失性存储器件包括基板和非易失性存储单元的3D阵列，3D阵列包括通过绝缘层彼此分离的多个导电层，多个导电层包括顶层，顶部 层包括n个字符串选择行（SSL）和一个或多个底层，顶层还包括n-1个切割，每个切割电隔离两个SSL，其中每个切割被切割到顶层的深度并且不延伸到 底层和与多个层正交布置的多个垂直通道，多个通道中的每一个包括一串存储器单元，多个串中的每一个耦合到位线，SSL和一个或多个字线。

公开(公告)号：US09437612B1

公开(公告)日：2016-09-06

申请号：US14832220

申请日：2015-08-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Lee ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L29/10 ,  H01L27/115 ,  H01L29/16 ,  H01L29/04 ,  H01L29/49 ,  H01L29/51 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/7889 ,  H01L29/7926

Abstract: A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.

Abstract translation: 三维存储器，其包括存储单元堆叠结构。 存储单元堆叠结构由多个存储单元阵列结构和绝缘层交替堆叠，并且每个存储单元阵列结构包括字线，有源层，复合层和源极/漏极。 字线，有源层和复合层沿Y方向延伸。 有源层设置在相邻字线之间。 复合层设置在相邻字线和相邻有源层之间，并且每个复合层从有源层依次包括第一介电层，电荷存储层和第二介质层。 源/排水口以相等的间隔设置在活性层中。 存储单元包括两个相邻的源/漏极，两个相邻源极/漏极之间的有源层，有源层上的第一介电层，电荷存储层和第二介电层以及字线。

公开(公告)号：US20190080750A1

公开(公告)日：2019-03-14

申请号：US15698812

申请日：2017-09-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Ta-Wei Lin ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Wen-Jer Tsai

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

公开(公告)号：US09859007B2

公开(公告)日：2018-01-02

申请号：US14742054

申请日：2015-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.

公开(公告)号：US09773554B2

公开(公告)日：2017-09-26

申请号：US14242757

申请日：2014-04-01

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Lee ,  Tien-Fan Ou ,  Jyun-Siang Huang ,  Chien-Hung Liu

IPC: H01L27/11 ,  H01L27/112 ,  G11C16/04 ,  H01L27/11568 ,  H01L21/265 ,  H01L29/10 ,  H01L29/167

CPC classification number: G11C16/0491 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L27/11568 ,  H01L29/1045 ,  H01L29/167

Abstract: An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.

公开(公告)号：US09589982B1

公开(公告)日：2017-03-07

申请号：US14854383

申请日：2015-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Shaw-Hung Ku ,  Wen-Pin Lu

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.

Abstract translation: 本发明的实施例提供改进的三维存储器单元，阵列，器件和/或类似物以及相关联的方法。 在一个实施例中，提供三维存储单元。 三维存储单元包括第一导电层; 与所述第一导电层间隔开的第三导电层; 连接第一导电层和第三导电层以形成具有内表面的开口的沟道导电层; 沿着由所述第一导电层，所述沟道导电层和所述第三导电层包围的所述开口的内表面设置的电介质层; 以及插入并基本上填充由电介质层形成的剩余开口部分的第二导电层。 第一导电层，电介质层和第二导电层被配置成形成阶梯结构。