公开(公告)号：US20250157548A1

公开(公告)日：2025-05-15

申请号：US18610368

申请日：2024-03-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Huai-Mu WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Chih-Chang HSIEH ,  Shang-Ting LIN

IPC: G11C16/26 ,  G11C16/04

Abstract: The disclosure discloses a memory device and an operation method thereof. A target memory cell and at least one replicated memory cell belonging to the same memory string are selected. A target weight value written into the target memory cell is replicated to the at least one replicated memory cell, wherein the target memory cell and the at least one replicated memory cell store the target weight value. In response to a command of reading or computing on the target memory cell received by the memory device, reading or computing is performed on the target memory cell and the at least one replicated memory cell simultaneously.

公开(公告)号：US20160267987A1

公开(公告)日：2016-09-15

申请号：US14657084

申请日：2015-03-13

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Chang HSIEH ,  Ti Wen CHEN ,  Yungchun Li ,  Hang Ting LUE

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/3427 ,  G11C16/3459

Abstract: This disclosure provides a memory device. The memory device includes a plurality of memory cells and a control circuit coupled to the memory cells. The control circuit is configured to provide a first programming voltage to the memory cells; verify the memory cells against an interim level verify voltage to divide the memory cells into a first group of memory cells and a second group of memory cells according to whether the memory cells do not reach or do reach the interim level verify voltage, respectively; provide a second programming voltage to the first group of memory cells and inhibit the second group of memory cells from receiving the second programming voltage, the second programming voltage being greater than or equal to the first programming voltage; and verify the first group of memory cells and the second group of memory cells against a desired level voltage.

Abstract translation: 本公开提供了一种存储器件。 存储器件包括多个存储器单元和耦合到存储器单元的控制电路。 控制电路被配置为向存储器单元提供第一编程电压; 根据存储器单元是否没有达到或确实达到临时电平验证电压，将存储器单元验证存储器单元抵消临时级验证电压以将存储器单元划分为第一组存储器单元和第二组存储器单元; 向第一组存储器单元提供第二编程电压，并且禁止第二组存储器单元接收第二编程电压，第二编程电压大于或等于第一编程电压; 并且针对所需的电平电压验证第一组存储器单元和第二组存储器单元。

公开(公告)号：US20250158628A1

公开(公告)日：2025-05-15

申请号：US18736681

申请日：2024-06-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LI ,  Chih-Chang HSIEH ,  BO-RONG LIN ,  Huai-Mu WANG ,  Chih-Huai SHIH

IPC: H03M1/12 ,  H03M1/38 ,  H03M1/50

Abstract: An analog-to-digital conversion device, includes the following elements. A sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value. A latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value. The latches and the logic circuits are used to perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.