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    Boost circuit
    1.
    发明授权
    Boost circuit 有权
    升压电路

    公开(公告)号：US09391597B2

    公开(公告)日：2016-07-12

    申请号：US14077945

    申请日：2013-11-12

    Applicant: Macronix International Co., Ltd.

    Inventor： Chih-Ting Hu ,  Shin-Jang Shen ,  Yi-Ching Liu

    IPC: G05F1/10 ,  H03K5/003 ,  H03K3/356 ,  H02M3/07

    CPC classification number: H02M3/07 ,  H03K3/356104 ,  H03K5/003 ,  H03K5/05

    Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

    Abstract translation: 升压电路包括提供电源电压的电源轨，控制来自开关晶体管的源极的升压信号的输出的开关晶体管，以及定时和电压控制电路，其被配置为产生要应用于 开关晶体管的栅极。 EQ波形的电平为EQ高电平，EQ低电平低于EQ高电平，或EQ钳位电平在EQ低电平和EQ高电平之间。

    FLASH MEMORY DEVICE AND BIT LINE CHARGING METHOD THEREOF
    2.
    发明申请
    FLASH MEMORY DEVICE AND BIT LINE CHARGING METHOD THEREOF 有权

    公开(公告)号：US20210375369A1

    公开(公告)日：2021-12-02

    申请号：US16888233

    申请日：2020-05-29

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chih-Ting Hu

    IPC: G11C16/24 ,  G11C16/04 ,  G11C16/30 ,  G11C16/10 ,  G11C16/08

    Abstract: A flash memory device includes a memory string, a selection switch, a first power source and a second power source. The memory string has a plurality of memory cells. A first memory cell in the memory string is coupled to a first word line, and the first word line is selected to be a programmed word line and the first memory cell is selected to be an inhibited cell, during a first time period, the selection switch is turned on according to a selection signal, and the first power source pulls up voltages on the global bit line and the local bit line to a first voltage. During a second time period, the selection switch is turned-off according to the selection signal, a word line voltage on the first word line is pulled up to pump up the voltage on the local bit line to a second voltage.

    Boost circuit
    3.
    发明授权
    Boost circuit 有权

    公开(公告)号：US10243454B2

    公开(公告)日：2019-03-26

    申请号：US15195732

    申请日：2016-06-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Chih-Ting Hu ,  Shin-Jang Shen ,  Yi-Ching Liu

    IPC: H03K5/003 ,  H02M3/07 ,  H03K3/356 ,  H03K5/05

    Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

    Capacitors in memory devices
    4.
    发明授权
    Capacitors in memory devices 有权

    公开(公告)号：US12200925B2

    公开(公告)日：2025-01-14

    申请号：US17723965

    申请日：2022-04-19

    Applicant: Macronix International Co., Ltd.

    Inventor： Jung-Chuan Ting ,  Chih-Ting Hu

    IPC: H10B41/23 ,  H10B41/41

    Abstract: Methods, systems and apparatus for managing capacitors in memory devices, e.g., three-dimensional (3D) memory devices are provided. In one aspect, a capacitor includes: a first terminal, a second terminal conductively insulated from the first terminal, and a capacitance structure that includes a plurality of layers sequentially stacked together. At least one layer includes: one or more first conductive parts and one or more second conductive parts that are conductively insulated in the layer, the one or more first conductive parts being conductively coupled to the first terminal, the one or more second conductive parts being conductively coupled to the second terminal. The at least one layer is configured such that at least one of the one or more second conductive parts forms at least one subordinate capacitor with at least one adjacent first conductive part.

    CAPACITORS IN MEMORY DEVICES
    8.
    发明公开
    CAPACITORS IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20230337421A1

    公开(公告)日：2023-10-19

    申请号：US17723965

    申请日：2022-04-19

    Applicant: Macronix International Co., Ltd.

    Inventor： Jung-Chuan Ting ,  Chih-Ting Hu

    IPC: H01L27/11553 ,  H01L27/11529

    CPC classification number: H01L27/11553 ,  H01L27/11529

    Abstract: Methods, systems and apparatus for managing capacitors in memory devices, e.g., three-dimensional (3D) memory devices are provided. In one aspect, a capacitor includes: a first terminal, a second terminal conductively insulated from the first terminal, and a capacitance structure that includes a plurality of layers sequentially stacked together. At least one layer includes: one or more first conductive parts and one or more second conductive parts that are conductively insulated in the layer, the one or more first conductive parts being conductively coupled to the first terminal, the one or more second conductive parts being conductively coupled to the second terminal. The at least one layer is configured such that at least one of the one or more second conductive parts forms at least one subordinate capacitor with at least one adjacent first conductive part.

    Flash memory device and bit line charging method thereof
    9.
    发明授权
    Flash memory device and bit line charging method thereof 有权

    公开(公告)号：US11195584B1

    公开(公告)日：2021-12-07

    申请号：US16888233

    申请日：2020-05-29

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chih-Ting Hu

    IPC: G11C16/06 ,  G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

    Abstract: A flash memory device includes a memory string, a selection switch, a first power source and a second power source. The memory string has a plurality of memory cells. A first memory cell in the memory string is coupled to a first word line, and the first word line is selected to be a programmed word line and the first memory cell is selected to be an inhibited cell, during a first time period, the selection switch is turned on according to a selection signal, and the first power source pulls up voltages on the global bit line and the local bit line to a first voltage. During a second time period, the selection switch is turned-off according to the selection signal, a word line voltage on the first word line is pulled up to pump up the voltage on the local bit line to a second voltage.

    Boost Circuit
    10.
    发明申请
    Boost Circuit 有权
    升压电路

    公开(公告)号：US20150131344A1

    公开(公告)日：2015-05-14

    申请号：US14077945

    申请日：2013-11-12

    Applicant: Macronix International Co., Ltd.

    Inventor： Chih-Ting Hu ,  Shin-Jang Shen ,  Yi-Ching Liu

    IPC: H02M3/155

    CPC classification number: H02M3/07 ,  H03K3/356104 ,  H03K5/003 ,  H03K5/05

    Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

    Abstract translation: 升压电路包括提供电源电压的电源轨，控制来自开关晶体管的源极的升压信号的输出的开关晶体管，以及定时和电压控制电路，其被配置为产生要应用于 开关晶体管的栅极。 EQ波形的电平为EQ高电平，EQ低电平低于EQ高电平，或EQ钳位电平在EQ低电平和EQ高电平之间。

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