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公开(公告)号：US07937058B2
公开(公告)日：2011-05-03
申请号：US11550534
申请日：2006-10-18
IPC分类号： H04B1/10
CPC分类号： H04B1/30 , H03H11/1256 , H03H11/1291 , H03H2210/012 , H03H2210/015 , H03H2210/025 , H03H2210/036
摘要： A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (409 and 411) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (253 and 254) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.
摘要翻译： 用于改变模拟滤波器（132）的截止频率的数字调谐系统（250）包括数字合成器（292和294），用于产生应用于滤波器的输入的双色调校信号（196） 过滤器增加。 滤波器包括至少一个R / C电路，其具有用于改变用于改变截止频率的电容器的品质因数和阵列（308和310）的两个电阻器（304和306）。 滤波器对每个音调（405和407）的幅度响应（409和411）的幅度通过两个离散的傅里叶变换单频率二次谐波频域功率检测电路（253和254）来测量，而滤波器通过多个 的电容设置。 对于每个电容设置，通过将滤波器的响应与每个音调的差值与预选值进行比较来选择R / C电路的最佳电容。
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2.发明授权Clock jitter minimization in a continuous time sigma delta analog-to-digital converter 有权连续时间Σ-Δ模数转换器中的时钟抖动最小化公开(公告)号：US07397291B1
公开(公告)日：2008-07-08
申请号：US11621844
申请日：2007-01-10
摘要： A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.
摘要翻译： 适用于连续时间Σ-Δ模数转换器中的反馈转换器的数 - 模转换器。 数模转换器具有离散时间数字信号输入，接受与第一数据时钟信号和离散时钟发生器的断言同步的数字信号采样，该离散时钟发生器响应于接收到第一数据信号的断言而产生输出脉冲 数据时钟。 输出脉冲被断言固定持续时间，与第一个数据时钟的抖动无关。 数模转换器还包括连续时间模拟输出，其在断言输出脉冲期间产生具有对应于数字信号采样的幅度的连续时间模拟输出信号。
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3.发明授权Signaling dependent adaptive analog-to-digital converter (ADC) system and method of using same 失效信号依赖自适应模数转换器（ADC）系统及其使用方法公开(公告)号：US06864817B1
公开(公告)日：2005-03-08
申请号：US10748543
申请日：2003-12-30
申请人： Raul Salvi , John J. Parkes, Jr. , James J. Riches
发明人： Raul Salvi , John J. Parkes, Jr. , James J. Riches
摘要： An adaptive analog-to-digital converter (ADC) system (100) includes an automatic gain control (AGC) controller (101) for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) (103) is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC (105). The ADC (105) uses the adjustment signal to dynamically control efficiency of the ADC system 100 by adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller (101).
摘要翻译： 自适应模数转换器（ADC）系统（100）包括自动增益控制（AGC）控制器（101），用于从射频（RF）接收器接收带内和带外信号，并产生 AGC控制信号。 数字信号处理器（DSP）（103）然后用于解释AGC控制信号并向ADC（105）提供调整信号。 ADC（105）使用调整信号通过基于接收到的RF信号和呈现给AGC控制器（101）的所需协议要求来调整位分辨率，参考电容和偏置来动态地控制ADC系统100的效率。
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公开(公告)号：US07629711B2
公开(公告)日：2009-12-08
申请号：US11690596
申请日：2007-03-23
申请人： Kai Zhong , John J. Parkes, Jr.
发明人： Kai Zhong , John J. Parkes, Jr.
CPC分类号： G05F1/56
摘要： An integrated circuit package (202) includes a voltage regulator (208) and a power-out pin (236) for coupling to a load circuit (210) via a connection (234) external to the integrated circuit package and for coupling to an output (230) of the voltage regulator via a connection (224, 228, 226 and 231) internal to the integrated circuit package. The internal connection has a series resistance that causes a voltage drop due to a load current. The voltage regulator compensates for the voltage drop in the internal connection using a current feedback circuit, in which the current fed back is proportional to the voltage drop caused by the series resistance of the internal connection.
摘要翻译： 集成电路封装（202）包括电压调节器（208）和电源输出引脚（236），用于经由集成电路封装外部的连接（234）耦合到负载电路（210），并用于耦合到输出 （230），经由集成电路封装内部的连接（224,228,226和231）。 内部连接具有由负载电流引起的电压降的串联电阻。 电压调节器使用电流反馈电路补偿内部连接中的电压降，其中反馈的电流与由内部连接的串联电阻引起的电压降成比例。
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公开(公告)号：US07723962B2
公开(公告)日：2010-05-25
申请号：US11690569
申请日：2007-03-23
申请人： John J. Parkes, Jr. , Kai Zhong
发明人： John J. Parkes, Jr. , Kai Zhong
CPC分类号： G05F1/571
摘要： A circuit includes a voltage regulator (208) for outputting a voltage at a regulated level, a protection circuit (260), and a load circuit (210) coupled to the voltage regulator. The protection circuit includes means for preventing the voltage regulator from outputting a voltage at a level higher than the regulated level during a start-up period of the voltage regulator.
摘要翻译： 电路包括用于输出调节电平的电压调节器（208），保护电路（260）和耦合到电压调节器的负载电路（210）。 保护电路包括用于在电压调节器的启动期间防止电压调节器输出高于调节电平的电平的装置。
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公开(公告)号：US07847524B2
公开(公告)日：2010-12-07
申请号：US12691301
申请日：2010-01-21
申请人： John J. Parkes, Jr. , Kai Zhong
发明人： John J. Parkes, Jr. , Kai Zhong
CPC分类号： G05F1/571
摘要： A circuit includes a voltage regulator (208) for outputting a voltage at a regulated level, a protection circuit (260), and a load circuit (210) coupled to the voltage regulator. The protection circuit includes means for preventing the voltage regulator from outputting a voltage at a level higher than the regulated level during a start-up period of the voltage regulator.
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公开(公告)号：US5545970A
公开(公告)日：1996-08-13
申请号：US283330
申请日：1994-08-01
CPC分类号： G05F1/573 , H02J7/0029
摘要： A voltage regulator circuit (100) for coupling to a power supply voltage (BPLUS) generates and regulates an output voltage (VREG). The voltage regulator circuit (100) includes a gain control element (148) for controlling the loop gain of the voltage regulator circuit (100) in response to the output current. Under heavy load conditions, the gain control element (148) functions to reduce (716) the output voltage (VREG) and thus the output current of the voltage regulator circuit (100) to avoid an overload that would pull the power supply voltage (BPLUS) below a predetermined level.
摘要翻译： 用于耦合到电源电压（BPLUS）的稳压器电路（100）产生并调节输出电压（VREG）。 电压调节器电路（100）包括用于响应于输出电流来控制电压调节器电路（100）的环路增益的增益控制元件（148）。 在重负载条件下，增益控制元件（148）用于减小（716）输出电压（VREG），从而降低调压器电路（100）的输出电流，以避免会导致电源电压（BPLUS ）低于预定水平。
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8.发明授权Low-voltage intermediate frequency amplifier providing automatic gain control of a source amplifier 失效提供源放大器的自动增益控制的低压中频放大器
公开(公告)号：US5481226A
公开(公告)日：1996-01-02
申请号：US329103
申请日：1994-10-25
申请人： John J. Parkes, Jr.
发明人： John J. Parkes, Jr.
CPC分类号： H03G3/3052
摘要： A low-voltage IF amplifier (112) provides automatic gain control (AGC) of a source amplifier (104) supplying an IF input signal to the IF amplifier (112). The IF amplifier (112) includes cascaded amplifier stages (202) that include an amplifier element (344) having an input (122) for receiving a stage input signal, and an output (124) for generating an amplified stage output signal in response. The amplifier stages (202) also include a received signal strength detector (346), or RSSD, for generating a gain control current responsive to the stage input signal. The IF amplifier (112) also includes a current summer (206) for summing the gain control currents generated by the RSSDs (346) to produce a total gain control current, and a gain control element (204) that controls the gain of the source amplifier (104) in response to the total gain control current, such that signal levels within the source amplifier (104) are maintained within a linear operating range.
摘要翻译： 低压IF放大器（112）提供向IF放大器（112）提供IF输入信号的源放大器（104）的自动增益控制（AGC）。 IF放大器（112）包括级联放大器级（202），其包括具有用于接收级输入信号的输入端（122）的放大器元件（344）和用于响应地产生放大级输出信号的输出端（124）。 放大器级（202）还包括接收信号强度检测器（346）或RSSD，用于响应于级输入信号产生增益控制电流。 IF放大器（112）还包括用于对由RSSD（346）产生的增益控制电流求和以产生总增益控制电流的电流加法器（206），以及控制源的增益的增益控制元件（204） 放大器（104），以使源放大器（104）内的信号电平保持在线性工作范围内。
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公开(公告)号：US5300937A
公开(公告)日：1994-04-05
申请号：US948078
申请日：1992-09-21
摘要： An antenna system maximizes a gain associated an antenna loop by expanding a free end away from a fixed end of the loop in response to first and second portions of the antenna loop resiliently engaging first and second interior sides of a housing to maintain the position of the antenna loop and increase the effective area of the antenna loop.
摘要翻译： 天线系统通过响应于天线环的第一和第二部分弹性地接合外壳的第一和第二内侧使自由端远离环路的固定端而使天线回路相关联，从而使天线回路最大化，以保持天线的位置 天线回路并增加天线回路的有效面积。
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10.发明授权
公开(公告)号：US5263192A
公开(公告)日：1993-11-16
申请号：US863892
申请日：1992-04-06
CPC分类号： H03H11/08
摘要： A filter (13) for providing temperature compensation for the quality factor thereof comprises transconductance amplifiers (23 and 24) in a gyrator configuration coupled between an input node (21) and an output node (22). A parallel capacitor (25) is coupled between the input node (21) and a supply voltage, and a parallel resistor (26) is coupled between the input node (21) and the supply voltage. A series capacitor (27) is coupled to the output node (22), and a series resistor (28) is coupled between the second capacitor (27) and the supply voltage.
摘要翻译： 用于为其品质因数提供温度补偿的滤波器（13）包括耦合在输入节点（21）和输出节点（22）之间的回转器配置中的跨导放大器（23和24）。 并联电容器（25）耦合在输入节点（21）和电源电压之间，并联电阻器（26）耦合在输入节点（21）和电源电压之间。 串联电容器（27）耦合到输出节点（22），串联电阻器（28）耦合在第二电容器（27）和电源电压之间。
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