公开(公告)号：US5027327A

公开(公告)日：1991-06-25

申请号：US339661

申请日：1989-04-18

申请人： Makiji Kobayashi ,  Mitsuo Isobe ,  Tatsuya Inatsuki ,  Hisashi Ueno

发明人： Makiji Kobayashi ,  Mitsuo Isobe ,  Tatsuya Inatsuki ,  Hisashi Ueno

IPC分类号： G11C11/403 ,  G11C11/406 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/406

摘要： A semiconductor memory having dynamic memory cells includes a determining circuit for determining whether or not it is necessary to refresh the dynamic memory cells, and only when it is necessary, outputting a refresh execution signal in response to a refresh request signal from an external circuit, and a circuit for executing a refresh operation in response to the refresh execution signal. Even if the refresh request signal is supplied, a refresh operation is not executed unless the determining circuit determines that the refresh operation is necessary, thus dispensing with unnecessary refresh operations. Preferably, the determining circuit includes a timer which outputs a signal at every predetermined period. Only when the signal is output from the timer, is the refresh request signal from an external circuit accepted and the refresh execution signal output.

公开(公告)号：US4933579A

公开(公告)日：1990-06-12

申请号：US261209

申请日：1988-10-24

申请人： Mitsuo Isobe ,  Makiji Kobayashi

发明人： Mitsuo Isobe ,  Makiji Kobayashi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/00361

摘要： An output circuit for outputting an output signal in response to an input signal having first and second voltage levels, comprises first circuit responsive to the input signal for generating a first signal including a low impedance portion corresponding to the duration of the second level of the input signal. A second circuit responsive to the input signal is further provided to supply a second signal including a low impedance portion which exists after the duration of the second voltage level of the input signal. The first and the second signals are combined to produce the output signal.

摘要翻译： 一种用于响应于具有第一和第二电压电平的输入信号而输出输出信号的输出电路，包括响应于输入信号的第一电路，用于产生第一信号，该第一信号包括对应于输入的第二电平的持续时间的低阻抗部分 信号。 还提供响应于输入信号的第二电路以提供包括在输入信号的第二电压电平的持续时间之后存在的低阻抗部分的第二信号。 第一和第二信号被组合以产生输出信号。

公开(公告)号：US4479191A

公开(公告)日：1984-10-23

申请号：US283015

申请日：1981-07-13

申请人： Minejiro Nojima ,  Makiji Kobayashi ,  Atsushi Kobayashi

发明人： Minejiro Nojima ,  Makiji Kobayashi ,  Atsushi Kobayashi

IPC分类号： G06F1/32 ,  H03K3/03 ,  G06F1/04

CPC分类号： G06F1/3228 ,  H03K3/03

摘要： A semiconductor integrated circuit which is capable of being selectively set to an operation mode or a stand-by mode has an oscillating circuit for outputting a frequency signal for controlling the operation of said semiconductor circuit. The output side of the oscillating circuit is connected to a timing generator through a first NAND gate. To the other input terminal of the first NAND gate is supplied information of an oscillation stop request (stand-by mode) due to reduction of the voltage of a power supply connected to the outside of the semiconductor integrated circuit and an oscillation start request (operation mode) accompanying the recovery of the voltage supply circuit or the oscillation from the timing generator through a second NAND gate. Thus, when the supply voltage is reduced, a logic low level signal is supplied from the second NAND gate to the first NAND gate to block the output of the oscillating circuit.A counter is connected to the oscillating circuit. When the supply voltage is recovered, the output of the oscillating circuit is supplied to the counter to be counted thereby. After the count reaches a predetermined number corresponding to a period sufficient to obtain a stable oscillation frequency output, an H flag is reset by a carry from the counter, whereupon a signal from the H Flag is supplied to the timing generator to cause the resumption of the operation of the timing generator.

摘要翻译： 能够被选择性地设置为操作模式或待机模式的半导体集成电路具有用于输出用于控制所述半导体电路的操作的频率信号的振荡电路。 振荡电路的输出端通过第一与非门连接到定时发生器。 由于连接到半导体集成电路的外部的电源的电压的降低和振荡开始请求（操作），向第一NAND门的另一输入端提供振荡停止请求（待机模式）的信息 模式），伴随着电压供应电路的恢复或来自定时发生器的振荡通过第二NAND门。 因此，当电源电压降低时，逻辑低电平信号从第二与非门提供给第一与非门，以阻止振荡电路的输出。 计数器连接到振荡电路。 当电源电压恢复时，振荡电路的输出被提供给计数器，从而被计数。 在计数达到对应于足以获得稳定的振荡频率输出的时间段的预定数量之后，通过来自计数器的进位来复位H标志，由此将来自H标志的信号提供给定时发生器以使恢复 定时发生器的运行。