-
1.发明授权Drive circuit of display apparatus, pulse generation method, display apparatus 有权显示装置的驱动电路，脉冲发生方法，显示装置公开(公告)号：US08098226B2
公开(公告)日：2012-01-17
申请号：US11921651
申请日：2006-06-12
IPC分类号： G09G3/36
CPC分类号： G09G3/3688
摘要： The subject invention provides a drive circuit for a display apparatus, comprising: a shift register; and a pulse generation circuit for generating a drive pulse signal using an output pulse signal generated in the shift register, wherein: the pulse generation circuit forms a pulse-starting edge and a pulse-termination edge of the drive pulse signal using a rise or a fall of pulse resulting from activation of the output pulse signal. On this account, pulse generation can be performed with high accuracy in a pulse generation circuit used for a drive circuit for a display apparatus or the like.
摘要翻译： 本发明提供了一种用于显示装置的驱动电路，包括：移位寄存器; 以及脉冲发生电路，用于使用在所述移位寄存器中产生的输出脉冲信号来产生驱动脉冲信号，其中：所述脉冲发生电路使用上升沿或者相对的方向形成所述驱动脉冲信号的脉冲起始边沿和脉冲终止边沿 由于输出脉冲信号的激活而产生的脉冲下降。 因此，在用于显示装置的驱动电路等的脉冲发生电路中，可以高精度地进行脉冲发生。
-
2.发明申请Drive Circuit of Display Apparatus, Pulse Generation Method, Display Apparatus 有权显示装置的驱动电路，脉冲发生方法，显示装置公开(公告)号：US20090115758A1
公开(公告)日：2009-05-07
申请号：US11921651
申请日：2006-06-12
IPC分类号： G06F3/038
CPC分类号： G09G3/3688
摘要： The subject invention provides a drive circuit for a display apparatus, comprising: a shift register; and a pulse generation circuit for generating a drive pulse signal using an output pulse signal generated in the shift register, wherein: the pulse generation circuit forms a pulse-starting edge and a pulse-termination edge of the drive pulse signal using a rise or a fall of pulse resulting from activation of the output pulse signal. On this account, pulse generation can be performed with high accuracy in a pulse generation circuit used for a drive circuit for a display apparatus or the like.
摘要翻译： 本发明提供了一种用于显示装置的驱动电路，包括：移位寄存器; 以及脉冲发生电路，用于使用在所述移位寄存器中产生的输出脉冲信号来产生驱动脉冲信号，其中：所述脉冲发生电路使用上升沿或者相对的方向形成所述驱动脉冲信号的脉冲起始边沿和脉冲终止边沿 由于输出脉冲信号的激活而产生的脉冲下降。 因此，在用于显示装置的驱动电路等的脉冲发生电路中，可以高精度地进行脉冲发生。
-
3.发明授权Pulse output circuit, driving circuit for display device and display device using the pulse output circuit, and pulse output method 失效脉冲输出电路，显示装置的驱动电路和使用脉冲输出电路的显示装置，以及脉冲输出方式公开(公告)号：US07786968B2
公开(公告)日：2010-08-31
申请号：US11002684
申请日：2004-12-03
IPC分类号： H03M1/50
CPC分类号： G09G3/3688 , G09G2310/0289 , G09G2310/0294
摘要： An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.
摘要翻译： 触发器的输出脉冲在提供给电平移位器的输入端子之前在延迟逆变器电路中被延迟。 然后，下一级触发器的输出脉冲被提供给第一触发器的复位端，并且还提供给电平移位器的使能端。 此外，电平移位器输出采样脉冲，其开始端等于提供给输入端子的脉冲的起始端和等于提供给使能端的脉冲的开始和脉冲。 通过这种布置，本发明提供了一种脉冲输出电路，一种使用脉冲输出电路的显示装置的驱动电路，一种显示装置和一种脉冲输出方法，该方法减少脉冲终端的延迟，从而顺序地从 多个输出端子。
-
4.发明申请Pulse output circuit, driving circuit for display device and display device using the pulse output circuit, and pulse output method 失效脉冲输出电路，显示装置的驱动电路和使用脉冲输出电路的显示装置，以及脉冲输出方式公开(公告)号：US20050134352A1
公开(公告)日：2005-06-23
申请号：US11002684
申请日：2004-12-03
CPC分类号： G09G3/3688 , G09G2310/0289 , G09G2310/0294
摘要： An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.
摘要翻译： 触发器的输出脉冲在提供给电平移位器的输入端子之前在延迟逆变器电路中被延迟。 然后，下一级触发器的输出脉冲被提供给第一触发器的复位端，并且还提供给电平移位器的使能端。 此外，电平移位器输出采样脉冲，其开始端等于提供给输入端子的脉冲的起始端和等于提供给使能端的脉冲的开始和脉冲。 通过这种布置，本发明提供了一种脉冲输出电路，一种使用脉冲输出电路的显示装置的驱动电路，一种显示装置和一种脉冲输出方法，该方法减少脉冲终端的延迟，从而顺序地从 多个输出端子。
-
公开(公告)号：US20050088387A1
公开(公告)日：2005-04-28
申请号：US10941082
申请日：2004-09-15
CPC分类号： G09G3/3648 , G09G2310/0251 , G09G2310/0297 , G09G2320/0219
摘要： In each horizontal period, by switching ON switches respectively provided for three data signal lines for R, G and B in a group at the same time only in a predetermined period, the data signal lines in the group are preliminary charged to a predetermined potential at the same time before a data signal supply period. In a subsequent data signal supply period, respective switches of data signal lines for R, G and B are switched ON sequentially, to sequentially supply respective data for R, G and B to pixels on a scanning signal line as selected are supplied via data signal lines. As a result, in a display device driven by time-division based on a group of sequentially provided data signal lines, it is possible to suppress up-throw potential fluctuations when display.
摘要翻译： 在每个水平周期中，通过仅在预定周期内同时分别为组中的R，G和B的三条数据信号线分别设置ON开关，将组中的数据信号线预先充电至预定电位 在数据信号提供期之前的同一时间。 在随后的数据信号供给周期中，对于R，G，B的数据信号线的各自的开关顺序地接通，顺序地向R，G，B的各个数据提供经选择的扫描信号线上的像素，经由数据信号 线条。 结果，在基于一组顺序提供的数据信号线的时分驱动的显示装置中，可以抑制显示时的上投电位波动。
-
公开(公告)号：US07701426B2
公开(公告)日：2010-04-20
申请号：US10941082
申请日：2004-09-15
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2310/0251 , G09G2310/0297 , G09G2320/0219
摘要： In each horizontal period, by switching ON switches respectively provided for three data signal lines for R, G and B in a group at the same time only in a predetermined period, the data signal lines in the group are preliminary charged to a predetermined potential at the same time before a data signal supply period. In a subsequent data signal supply period, respective switches of data signal lines for R, G and B are switched ON sequentially, to sequentially supply respective data for R, G and B to pixels on a scanning signal line as selected are supplied via data signal lines. As a result, in a display device driven by time-division based on a group of sequentially provided data signal lines, it is possible to suppress up-throw potential fluctuations when display.
摘要翻译： 在每个水平周期中，通过仅在预定周期内同时分别为组中的R，G和B的三条数据信号线分别设置ON开关，将组中的数据信号线预先充电至预定电位 在数据信号提供期之前的同一时间。 在随后的数据信号供给周期中，对于R，G，B的数据信号线的各自的开关顺序地接通，顺序地向R，G，B的各个数据提供经选择的扫描信号线上的像素，经由数据信号 线条。 结果，在基于一组顺序提供的数据信号线的时分驱动的显示装置中，可以抑制显示时的上投电位波动。
-
公开(公告)号：US20090115716A1
公开(公告)日：2009-05-07
申请号：US11921116
申请日：2006-06-12
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0232 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2340/0442 , G11C19/28
摘要： In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.
摘要翻译： 在本发明的一个实施例中，本移位寄存器是设置在显示设备中的移位寄存器，通过该移位寄存器可以获得部分屏幕显示。 移位寄存器包括设置在中间级中的移位停止电路，并且在部分屏幕显示中停止移位寄存器的第一级和最后级之间的移位寄存器的操作。 移位寄存器还包括一个电路，其被提供在除了中间级之外的阶段中，使得该电路不执行信号处理而用作信号路径。 该电路与配置中的换挡停止电路相同。 上述可以改善采用本移位寄存器的显示装置的显示质量。
-
公开(公告)号：US20070242021A1
公开(公告)日：2007-10-18
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.
-
公开(公告)号：US20050175138A1
公开(公告)日：2005-08-11
申请号：US11044003
申请日：2005-01-28
CPC分类号： G09G3/3688 , G11C19/00 , G11C19/28
摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.
摘要翻译： 在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。 相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并且生成从其重叠部分被去除的输出信号A（A 1，A 2，...）。 波形定时形成部输出通过提取在对应的相位差检测部中产生的输出信号A（A 1，A 2，...）的周期而获得的输出信号X（X 1，X 2，...） 当来自相应触发器的输出信号Q（Q 1，Q 2，...）为高时，为高电平。 输出信号X（X 1，X 2，...）在下一阶段设置触发器。 根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。 也可以实现具有移位寄存器的显示装置。
-
公开(公告)号：US07505022B2
公开(公告)日：2009-03-17
申请号：US11044003
申请日：2005-01-28
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G11C19/00 , G11C19/28
摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.
摘要翻译： 在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。 相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并产生从其重叠部分被去除的输出信号A（A1，A2 ...）。 波形定时形成部输出通过提取在相应的相位差检测部中产生的输出信号A（A1，A2 ......）的高电平的期间而获得的输出信号X（X1，X2 ...），当 来自相应触发器的输出信号Q（Q1，Q2 ...）为高。 输出信号X（X1，X2，...）在下一阶段设置触发器。 根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。 也可以实现具有移位寄存器的显示装置。
-
-
-
-
-
-
-
-
-
搜索结果
110 条记录 (耗时 0.028 秒)