-
公开(公告)号：US20050088387A1
公开(公告)日：2005-04-28
申请号：US10941082
申请日：2004-09-15
CPC分类号： G09G3/3648 , G09G2310/0251 , G09G2310/0297 , G09G2320/0219
摘要： In each horizontal period, by switching ON switches respectively provided for three data signal lines for R, G and B in a group at the same time only in a predetermined period, the data signal lines in the group are preliminary charged to a predetermined potential at the same time before a data signal supply period. In a subsequent data signal supply period, respective switches of data signal lines for R, G and B are switched ON sequentially, to sequentially supply respective data for R, G and B to pixels on a scanning signal line as selected are supplied via data signal lines. As a result, in a display device driven by time-division based on a group of sequentially provided data signal lines, it is possible to suppress up-throw potential fluctuations when display.
摘要翻译： 在每个水平周期中，通过仅在预定周期内同时分别为组中的R，G和B的三条数据信号线分别设置ON开关，将组中的数据信号线预先充电至预定电位 在数据信号提供期之前的同一时间。 在随后的数据信号供给周期中，对于R，G，B的数据信号线的各自的开关顺序地接通，顺序地向R，G，B的各个数据提供经选择的扫描信号线上的像素，经由数据信号 线条。 结果，在基于一组顺序提供的数据信号线的时分驱动的显示装置中，可以抑制显示时的上投电位波动。
-
公开(公告)号：US07701426B2
公开(公告)日：2010-04-20
申请号：US10941082
申请日：2004-09-15
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2310/0251 , G09G2310/0297 , G09G2320/0219
摘要： In each horizontal period, by switching ON switches respectively provided for three data signal lines for R, G and B in a group at the same time only in a predetermined period, the data signal lines in the group are preliminary charged to a predetermined potential at the same time before a data signal supply period. In a subsequent data signal supply period, respective switches of data signal lines for R, G and B are switched ON sequentially, to sequentially supply respective data for R, G and B to pixels on a scanning signal line as selected are supplied via data signal lines. As a result, in a display device driven by time-division based on a group of sequentially provided data signal lines, it is possible to suppress up-throw potential fluctuations when display.
摘要翻译： 在每个水平周期中，通过仅在预定周期内同时分别为组中的R，G和B的三条数据信号线分别设置ON开关，将组中的数据信号线预先充电至预定电位 在数据信号提供期之前的同一时间。 在随后的数据信号供给周期中，对于R，G，B的数据信号线的各自的开关顺序地接通，顺序地向R，G，B的各个数据提供经选择的扫描信号线上的像素，经由数据信号 线条。 结果，在基于一组顺序提供的数据信号线的时分驱动的显示装置中，可以抑制显示时的上投电位波动。
-
3.发明授权Signal processing circuit, inverter circuit, buffer circuit, level shifter, flip-flop, driver circuit, and display device 有权信号处理电路，逆变电路，缓冲电路，电平转换器，触发器，驱动电路和显示装置公开(公告)号：US08779809B2
公开(公告)日：2014-07-15
申请号：US13819400
申请日：2011-08-31
IPC分类号： H03K3/00
CPC分类号： H02J4/00 , H03K3/356008 , H03K3/356026 , H03K19/01714 , H03K19/01735 , Y10T307/50
摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source. This configuration can increase reliability of a bootstrap-type signal processing circuit.
摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 以及用于控制自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子，所述电荷控制部分和所述第一输出部分经由继电器部分彼此连接，用于任一 将电荷控制部和第一输出部彼此电连接，或者将电荷控制部和第一输出部彼此电阻塞，电荷控制部包括与第二电源连接的电阻。 该配置可以增加自举式信号处理电路的可靠性。
-
4.发明授权公开(公告)号：US08736534B2
公开(公告)日：2014-05-27
申请号：US11922491
申请日：2006-07-11
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0245 , G09G2330/02 , G09G2330/027
摘要： In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.
摘要翻译： 在本发明的一个实施例中，在每个源极总线上，设置电荷逸出晶体管，其具有与像素晶体管相同的极性，并且具有提供像素晶体管的关断电压信号的栅极。 当有源矩阵液晶显示装置断电时，在像素晶体管的导通电压信号达到GND电平之前，使关断电压信号达到GND电平，使得像素晶体管和电荷 逃逸晶体管制成半开放。 这使得在像素中累积的电荷逃逸到公共电极TCOM。
-
5.发明申请SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE 有权信号处理电路，逆变器电路，缓冲电路，驱动电路，电平变换器和显示装置公开(公告)号：US20130194033A1
公开(公告)日：2013-08-01
申请号：US13819043
申请日：2011-08-31
IPC分类号： G05F3/16
CPC分类号： G05F3/16 , G09G3/3674 , G09G2310/0286 , G09G2310/0291 , H04L25/0272
摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.
摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 用于控制所述自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子; 以及电阻器，其具有（i）连接到所述输出端子的第一端和（ii）连接到第二电源的第二端。 这种布置允许信号处理电路即使在自举效应已经磨损之后仍然保持输出电位。
-
公开(公告)号：US20130169319A1
公开(公告)日：2013-07-04
申请号：US13819827
申请日：2011-08-31
IPC分类号： H03K17/00
CPC分类号： H03K17/005 , G09G3/3677 , G09G2310/0286 , G09G2310/08 , G11C19/184 , G11C19/28 , H03K19/00315
摘要： A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit.
摘要翻译： 本发明的信号处理电路包括：第一输入端; 第二输入端; 第三输入端; 第一个节点; 第二个节点; 输出端子; 一个电阻; （i）连接到第一节点的第一信号产生部分，第三输入端子和输出端子，以及（ii）包括自举电容器; 以及连接到第二节点的第二信号产生部分，第一电源和输出端子。 在第一输入端子变为活动状态的情况下，第一节点变为活动状态。 在第二输入端子变为活动状态的情况下，第二节点变为活动状态。 输出端子通过电阻连接到第一个电源。 利用该配置，可以改善信号处理电路的操作稳定性。
-
7.发明授权Signal output circuit, shift register, output signal generating method, display device driving circuit, and display device 有权信号输出电路，移位寄存器，输出信号生成方法，显示装置驱动电路和显示装置公开(公告)号：US08344988B2
公开(公告)日：2013-01-01
申请号：US11922345
申请日：2006-07-13
IPC分类号： G09G3/36
摘要： A signal output circuit of one embodiment of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.
摘要翻译： 本发明的一个实施例的信号输出电路设置在移位寄存器的单元级中。 信号输出电路包括设置复位触发器和信号产生电路，用于根据输入的信号通过加载或阻塞时钟信号来产生输出信号。 信号输出电路被布置为：信号发生电路接收从触发器输出的信号和反馈到信号发生电路的输出信号; 并将输出信号反馈到触发器的复位输入。 这使得可以实现电路面积的减小和电路的简化。
-
公开(公告)号：US20120200614A1
公开(公告)日：2012-08-09
申请号：US13501368
申请日：2010-06-02
CPC分类号： G09G3/3614 , G09G3/3655 , G09G3/3674 , G09G3/3677 , G09G2300/0876 , G09G2310/0264 , G09G2310/0286 , G09G2310/08 , G09G2320/0219 , G09G2320/0233 , G09G2340/0407
摘要： In a display device (i) which carries out a display based on a video signal whose resolution has been converted to higher resolution (high-resolution conversion driving) and (ii) which carries out CC driving, when the resolution of the video signal is converted by a factor of 2 (double-size display), assuming that a direction in which the gate lines extend is a row-wise direction, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent gate lines and that are adjacent to each other in the column-wise direction (scanning direction), and a direction of change in the signal potentials written to the pixel electrodes from the source lines varies every two adjacent rows according to the polarities of the signal potentials.
摘要翻译： 在基于分辨率被转换为更高分辨率（高分辨率转换驱动）的视频信号和执行CC驱动的（ii））执行显示的显示装置（i）中，当视频信号的分辨率为 转换为2倍（双倍尺寸显示），假设栅极线延伸的方向是行方向，具有相同极性和相同灰度的信号电位被提供给包括在相应两个中的像素电极 对应于两个相邻的栅极线并且在列方向（扫描方向）上彼此相邻的像素，并且从源极线写入像素电极的信号电位的变化方向根据 到信号电位的极性。
-
公开(公告)号：US20120086689A1
公开(公告)日：2012-04-12
申请号：US13377847
申请日：2010-02-28
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3659 , G09G3/3677 , G09G2300/0852 , G09G2320/0247
摘要： An embodiment of the present invention switches, in a display driving circuit of a liquid crystal display device which carries out CC driving, between a two-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every two horizontal scanning periods and a one-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every one horizontal scanning period. In at least one example embodiment, a polarity signal reverses its polarity every two horizontal scanning periods in the two-line reversal driving mode, and reverses its polarity every one horizontal scanning period in the one-line reversal driving mode.
摘要翻译： 本发明的一个实施例在执行CC驱动的液晶显示装置的显示驱动电路中，在提供给源极线的数据信号的极性每二次反转的两线反向驱动模式之间切换 水平扫描周期和提供给源极线的数据信号的极性在每一个水平扫描周期反转的单线反转驱动模式。 在至少一个示例性实施例中，极性信号在双线反向驱动模式中每两个水平扫描周期反转其极性，并且在单行反向驱动模式中每一个水平扫描周期反转其极性。
-
公开(公告)号：US20100309184A1
公开(公告)日：2010-12-09
申请号：US12734595
申请日：2008-08-20
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0289 , G11C19/28 , H01L27/124 , H03K17/161 , H03K17/162 , H03K17/687
摘要： A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.
摘要翻译： 在至少一个实施例中，由多个n沟道晶体管构成的电路包括具有供给输入信号的漏极端子和提供输出信号的源极端子的晶体管（T1）; 以及具有提供控制信号的漏极端子和与晶体管（T1）的栅极端子连接的源极端子的晶体管（T2）。 晶体管（T2）的栅极端子连接到晶体管（T2）的源极端子。 通过该结构，可以提供（i）由具有相同导电类型并能够减小噪声影响的晶体管构成的半导体器件，以及（ii）包括半导体器件的显示器件。
-
-
-
-
-
-
-
-
-
搜索结果
60 条记录 (耗时 0.035 秒)
