公开(公告)号：US5771047A

公开(公告)日：1998-06-23

申请号：US355517

申请日：1994-12-14

申请人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

发明人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

IPC分类号： G06T11/20 ,  G06T11/00

CPC分类号： G06T11/203

摘要： To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and a multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes a line drawing procedure that uses data tables and a multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data. Thus, the graphics computer hardware is reduced in size and the cost of the hardware is reduced.

摘要翻译： 为了减小图形计算机的硬件尺寸并降低硬件成本，将帧缓冲器和主存储器联合成一个单元来处理CPU中的图形数据。 帧缓冲器布置在主存储器中，并且图形计算机包括用于从帧缓冲器读取像素数据以进行显示的DMAC，用于接收像素数据并将其显示在诸如LCD的显示设备上的显示器， 以及用于存储CPU使用的程序来绘制所述帧缓冲器中的像素数据的存储器。 特别地，所述存储器被形成为使得可以选择单个功能过程和多功能过程以适合绘图对象。 另外，单功能过程包括使用数据表的线条画过程和使用模式表和掩码表的多值扩展过程。 由于帧缓冲器和主存储器被组合成一个单元，所以CPU可以用于处理图形数据。 因此，图形计算机硬件的尺寸减小，硬件的成本降低。

公开(公告)号：US06677950B1

公开(公告)日：2004-01-13

申请号：US08996151

申请日：1997-12-22

申请人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

发明人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

IPC分类号： G06T1500

CPC分类号： G06T11/203

摘要： To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and 2 multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes 2 line drawing procedure that uses data tables and 2 multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data. Thus, the graphics computer hardware is reduced in size and the cost of the hardware is reduced.

摘要翻译： 为了减小图形计算机的硬件尺寸并降低硬件成本，将帧缓冲器和主存储器联合成一个单元来处理CPU中的图形数据。 帧缓冲器布置在主存储器中，并且图形计算机包括用于从帧缓冲器读取像素数据以进行显示的DMAC，用于接收像素数据并将其显示在诸如LCD的显示设备上的显示器， 以及用于存储CPU使用的程序来绘制所述帧缓冲器中的像素数据的存储器。 特别地，所述存储器被形成为使得可以选择单个功能过程和2多功能过程以适合绘图对象。 另外，单功能过程包括使用数据表的2行绘图过程和使用模式表和掩码表的2多值扩展过程。 由于帧缓冲器和主存储器被组合成一个单元，所以CPU可以用于处理图形数据。 因此，图形计算机硬件的尺寸减小，硬件的成本降低。

公开(公告)号：US20100180140A1

公开(公告)日：2010-07-15

申请号：US12731442

申请日：2010-03-25

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F1/12

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US20080168295A1

公开(公告)日：2008-07-10

申请号：US11826136

申请日：2007-07-13

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F1/06

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US07254737B2

公开(公告)日：2007-08-07

申请号：US10897022

申请日：2004-07-23

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F1/04

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US06789210B2

公开(公告)日：2004-09-07

申请号：US10353910

申请日：2003-01-30

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F104

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US06785833B2

公开(公告)日：2004-08-31

申请号：US10368615

申请日：2003-02-20

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F104

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US08332683B2

公开(公告)日：2012-12-11

申请号：US12731442

申请日：2010-03-25

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F1/04

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US07711976B2

公开(公告)日：2010-05-04

申请号：US11826136

申请日：2007-07-13

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F1/04

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US06550014B2

公开(公告)日：2003-04-15

申请号：US10216179

申请日：2002-08-12

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F104

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.