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公开(公告)号：US06466221B1
公开(公告)日：2002-10-15
申请号：US09879045
申请日：2001-06-13
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G09G536
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。
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公开(公告)号：US06550014B2
公开(公告)日：2003-04-15
申请号：US10216179
申请日：2002-08-12
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F104
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
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公开(公告)号：US6097404A
公开(公告)日：2000-08-01
申请号：US357374
申请日：1999-07-20
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F3/153 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/12 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/00 , G06F13/14 , G06F13/16 , G06F15/00 , G06F15/76 , G06T1/00 , G06T1/20 , G06T1/60 , G09G5/36 , G09G5/393 , G11C5/00 , G11C11/401 , G11C11/407
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G09G5/399
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
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公开(公告)号：US5999197A
公开(公告)日：1999-12-07
申请号：US940632
申请日：1997-09-30
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F3/153 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/12 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/00 , G06F13/14 , G06F13/16 , G06F15/00 , G06F15/76 , G06T1/00 , G06T1/20 , G06T1/60 , G09G5/36 , G09G5/393 , G11C5/00 , G11C11/401 , G11C11/407
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G09G5/399
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。
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公开(公告)号：US20100180140A1
公开(公告)日：2010-07-15
申请号：US12731442
申请日：2010-03-25
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/12
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。
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公开(公告)号：US20080168295A1
公开(公告)日：2008-07-10
申请号：US11826136
申请日：2007-07-13
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。
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公开(公告)号：US07254737B2
公开(公告)日：2007-08-07
申请号：US10897022
申请日：2004-07-23
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/04
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。
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公开(公告)号：US06789210B2
公开(公告)日：2004-09-07
申请号：US10353910
申请日：2003-01-30
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F104
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。
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公开(公告)号：US06785833B2
公开(公告)日：2004-08-31
申请号：US10368615
申请日：2003-02-20
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F104
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。
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公开(公告)号：US08332683B2
公开(公告)日：2012-12-11
申请号：US12731442
申请日：2010-03-25
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/04
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。
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