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公开(公告)号：US06566718B2
公开(公告)日：2003-05-20
申请号：US09848085
申请日：2001-05-03
IPC分类号： H01L2976
CPC分类号： H01L23/5222 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor comprises a gate electrode contact of a highly conductive material that contacts the gate electrode and extends in the transistor width dimension at least along a portion of the channel. Thus, the gate resistance and the gate signal propagation time for a voltage applied to the gate contact is significantly reduced even for devices with an extremely down scaled gate length. Moreover, a method for fabricating the above FET is disclosed.
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2.发明授权Field effect transistor with reduced gate delay and method of fabricating the same 有权具有减小的栅极延迟的场效应晶体管及其制造方法公开(公告)号：US06798028B2
公开(公告)日：2004-09-28
申请号：US09847622
申请日：2001-05-02
IPC分类号： H01L2976
CPC分类号： H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/4933
摘要： A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.
摘要翻译： 形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。 与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是 缩小到100nm以上的尺寸。 此外，公开了一种用于形成上述场效应晶体管的方法。
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3.发明授权Method of forming different silicide portions on different silicon-containing regions in a semiconductor device 有权在半导体器件中在不同含硅区域上形成不同硅化物部分的方法公开(公告)号：US07226859B2
公开(公告)日：2007-06-05
申请号：US10282720
申请日：2002-10-29
IPC分类号： H01L29/40
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L29/4933
摘要： A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.
摘要翻译： 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着提高单个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。
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公开(公告)号：US07115464B2
公开(公告)日：2006-10-03
申请号：US10259016
申请日：2002-09-27
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/76 , H01L21/3205
CPC分类号： H01L21/324 , H01L21/28052 , H01L21/823835 , H01L21/823842
摘要： In a method for fabricating a semiconductor device different types of a metal-semiconductor compound are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be formed to obtain an optimum overall performance of the semiconductor device. On one of the two semiconductor regions, the metal-semiconductor compound is formed of at least two different metal layers, whereas the metal-semiconductor compound in or on the other semiconductor region is formed from a single metal layer.
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5.发明授权Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions 有权形成半导体结构的方法包括具有不同应力沟道区的晶体管元件公开(公告)号：US07238578B2
公开(公告)日：2007-07-03
申请号：US11114262
申请日：2005-04-26
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/823437 , H01L21/823807 , H01L21/823828 , H01L29/7843
摘要： A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.
摘要翻译： 提供包括第一晶体管元件和第二晶体管元件的半导体结构。 通过在晶体管上形成具有预定应力的应力层来控制第一和第二晶体管元件的沟道区域中的应力。 应力层可以用作通过在晶体管上形成的层间电介质形成接触孔的蚀刻停止层。
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6.发明授权Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same 有权在沟道区域具有逆向掺杂剂分布的半导体器件及其制造方法公开(公告)号：US06881641B2
公开(公告)日：2005-04-19
申请号：US10282980
申请日：2002-10-29
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L21/331
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/6659
摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
摘要翻译： 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。
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7.发明授权公开(公告)号：US06770552B2
公开(公告)日：2004-08-03
申请号：US10400706
申请日：2003-03-27
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6659
摘要： The cross-sectional area of polysilicon lines is increased by selectively epitaxially growing an upper portion of the polysilicon line in the presence of a dielectric layer exposing the upper portion. Thus, a substantially T-shaped line is obtained, allowing a minimum bottom-CD while insuring a sufficient high conductivity.
摘要翻译： 在存在暴露上部的电介质层的情况下，通过选择性地外延生长多晶硅线的上部来增加多晶硅线的横截面面积。 因此，获得基本上T形的线，允许最小的底部CD，同时确保足够的高导电性。
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公开(公告)号：US06492210B2
公开(公告)日：2002-12-10
申请号：US09810771
申请日：2001-03-16
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/66545 , H01L29/78621
摘要： This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.
摘要翻译： 本发明提供了在基于用于形成器件隔离特征和源极和漏极区域的栅电极和侧壁间隔物屏蔽程序的基础上使用自对准技术在集成电路中形成场效应晶体管的方法。 本发明能够增加半导体器件的积分密度，使场效应晶体管器件中的寄生电容最小化，以及更快的制造工艺。
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9.发明授权公开(公告)号：US07297994B2
公开(公告)日：2007-11-20
申请号：US11072142
申请日：2005-03-04
CPC分类号： H01L21/823807 , H01L29/1033 , H01L29/105 , H01L29/1054 , H01L29/6659
摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
摘要翻译： 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。
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10.发明授权Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device 有权具有不同金属硅化物部分的半导体器件和用于制造半导体器件的方法公开(公告)号：US07217657B2
公开(公告)日：2007-05-15
申请号：US10260926
申请日：2002-09-30
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/823418 , H01L21/823443 , H01L29/4933
摘要： A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.
摘要翻译： 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着改善各个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。
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