-
公开(公告)号:US20130109143A1
公开(公告)日:2013-05-02
申请号:US13572281
申请日:2012-08-10
申请人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan , John Xia
发明人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan , John Xia
IPC分类号: H01L29/78
CPC分类号: H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.
摘要翻译: 本申请的特征在于在垂直横向扩散的金属氧化物半导体(LDMOS)晶体管中制造栅极区域的方法。 在一个方面,一种方法包括在植入在衬底上的n阱区域上沉积掩模层,图案化掩模层以限定区域,以及在该区域中形成第一沟槽,使得第一沟槽的长度从 n阱区域的表面到n阱区域中的第一深度。 该方法还包括通过导电材料填充第一沟槽并在该区域上沉积一层氧化物。 该方法还包括蚀刻掉氧化物层的至少一部分以暴露导电材料的一部分,从暴露部分去除导电材料以形成第二沟槽,并用氧化物填充第二沟槽以形成非对称栅极 的晶体管。
-
公开(公告)号:US08709899B2
公开(公告)日:2014-04-29
申请号:US13572281
申请日:2012-08-10
申请人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan , John Xia
发明人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan , John Xia
IPC分类号: H01L21/336
CPC分类号: H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要: The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.
摘要翻译: 本申请的特征在于在垂直横向扩散的金属氧化物半导体(LDMOS)晶体管中制造栅极区域的方法。 在一个方面,一种方法包括在植入在衬底上的n阱区域上沉积掩模层,图案化掩模层以限定区域,以及在该区域中形成第一沟槽,使得第一沟槽的长度从 n阱区域的表面到n阱区域中的第一深度。 该方法还包括通过导电材料填充第一沟槽并在该区域上沉积一层氧化物。 该方法还包括蚀刻掉氧化物层的至少一部分以暴露导电材料的一部分,从暴露部分去除导电材料以形成第二沟槽,并用氧化物填充第二沟槽以形成非对称栅极 的晶体管。
-
公开(公告)号:US10147801B2
公开(公告)日:2018-12-04
申请号:US13572110
申请日:2012-08-10
申请人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
IPC分类号: H01L29/66 , H01L29/78 , H01L29/06 , H01L21/8234 , H01L27/088 , H01L21/265 , H01L21/28 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/08 , H01L29/10
摘要: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.
-
公开(公告)号:US20130105887A1
公开(公告)日:2013-05-02
申请号:US13572015
申请日:2012-08-10
申请人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
CPC分类号: H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.
摘要翻译: 这里描述的是晶体管及其制造方法。 在一个实施方式中,晶体管包括注入到衬底的表面中的n阱区域和n阱区域中的沟槽。 沟槽从表面延伸到第一深度。 沟槽包括在沟槽中的导电材料的栅极,以及填充未被导电材料填充的一定体积的电介质材料。 晶体管还包括在从第二深度延伸到第三深度的第一区域中的p型材料,第二深度和第三深度大于第一深度。 晶体管还包括源极区和漏极区。
-
公开(公告)号:US20130105888A1
公开(公告)日:2013-05-02
申请号:US13572110
申请日:2012-08-10
申请人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
IPC分类号: H01L29/78
CPC分类号: H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.
摘要翻译: 本申请的特征在于一种晶体管,其包括注入到衬底,栅极区域和源极区域以及漏极区域的表面中的n阱区域。 源极区域在栅极区域的第一侧上,并且在n阱区域中包括p体区域。 在p体区域注入n +区域和p +区域,使得p +区域低于n +区域。 漏极区域在栅极区域的第二侧上并且包括n +区域。
-
公开(公告)号:US08866217B2
公开(公告)日:2014-10-21
申请号:US13572015
申请日:2012-08-10
申请人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
CPC分类号: H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.
摘要翻译: 这里描述的是晶体管及其制造方法。 在一个实施方式中,晶体管包括注入到衬底的表面中的n阱区域和n阱区域中的沟槽。 沟槽从表面延伸到第一深度。 沟槽包括在沟槽中的导电材料的栅极,以及填充未被导电材料填充的一定体积的电介质材料。 晶体管还包括在从第二深度延伸到第三深度的第一区域中的p型材料,第二深度和第三深度大于第一深度。 晶体管还包括源极区和漏极区。
-
公开(公告)号:US08647950B2
公开(公告)日:2014-02-11
申请号:US13572428
申请日:2012-08-10
申请人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
IPC分类号: H01L21/336
CPC分类号: H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
摘要翻译: 一种在LDMOS晶体管中制造垂直栅极区域的方法,包括在植入在衬底上的n阱区域上沉积第一掩模层,图案化第一掩模层以限定区域,在该区域上沉积第二掩模层, 在所述区域的第一部分中的第二掩模层以暴露所述n阱区域,以及蚀刻所暴露的n阱区域以形成第一沟槽。 从n阱区域的表面延伸到第一深度的第一沟槽被填充有氧化物。 在该区域的第二部分中蚀刻第二掩模层以暴露n阱区域。 在n阱中形成第二沟槽,第二沟槽从表面延伸到第二深度,小于第一深度。 通过用导电材料填充第二沟槽来形成非对称垂直栅极。
-
公开(公告)号:US20130115744A1
公开(公告)日:2013-05-09
申请号:US13572428
申请日:2012-08-10
申请人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人: Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
IPC分类号: H01L29/66
CPC分类号: H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要: A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
摘要翻译: 一种在LDMOS晶体管中制造垂直栅极区域的方法,包括在植入在衬底上的n阱区域上沉积第一掩模层,图案化第一掩模层以限定区域,在该区域上沉积第二掩模层, 在所述区域的第一部分中的第二掩模层以暴露所述n阱区域,以及蚀刻所暴露的n阱区域以形成第一沟槽。 从n阱区域的表面延伸到第一深度的第一沟槽被填充有氧化物。 在该区域的第二部分中蚀刻第二掩模层以暴露n阱区域。 在n阱中形成第二沟槽,第二沟槽从表面延伸到第二深度,小于第一深度。 通过用导电材料填充第二沟槽来形成非对称垂直栅极。
-
-
-
-
-
-
-