公开(公告)号：US20060245258A1

公开(公告)日：2006-11-02

申请号：US11396411

申请日：2006-03-31

申请人： Mario Saggio ,  Antonino Minnolo ,  Rosalia Germana

发明人： Mario Saggio ,  Antonino Minnolo ,  Rosalia Germana

IPC分类号： G11C11/34

CPC分类号： H01L29/0634 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/7803 ,  H01L29/7811

摘要： An integrated power device includes a semiconductor body of a first conductivity type comprising a first region accommodating a start-up structure, and a second region accommodating a power structure. The two structures are separated from one another by an edge structure and are arranged in a mirror configuration with respect to a symmetry line of the edge structure. Both the start-up structure and the power structure are obtained using MOSFET devices. Both MOSFET devices are multi-drain MOSFET devices, having mesh regions, source regions and gate regions separated from one another. In addition, both MOSFET devices have drain regions delimited by columns that repeat periodically at a fixed distance. Between the two MOSFET devices there is an electrical insulation of at least 25 V.

摘要翻译： 集成的功率器件包括第一导电类型的半导体本体，包括容纳启动结构的第一区域和容纳功率结构的第二区域。 这两个结构通过边缘结构彼此分离，并且相对于边缘结构的对称线布置成反射镜构造。 启动结构和功率结构均使用MOSFET器件获得。 两个MOSFET器件都是多漏极MOSFET器件，其具有彼此分离的网格区域，源极区域和栅极区域。 另外，两个MOSFET器件具有由固定距离周期性重复的列限定的漏极区域。 在两个MOSFET器件之间，电绝缘至少为25 V.

公开(公告)号：US20060194391A1

公开(公告)日：2006-08-31

申请号：US11362435

申请日：2006-02-23

申请人： Mario Saggio ,  Ferruccio Frisina

发明人： Mario Saggio ,  Ferruccio Frisina

IPC分类号： H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

摘要： A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.

公开(公告)号：US07071062B2

公开(公告)日：2006-07-04

申请号：US11023957

申请日：2004-12-28

申请人： Mario Saggio ,  Ferruccio Frisina

发明人： Mario Saggio ,  Ferruccio Frisina

IPC分类号： H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

摘要： An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor. The elementary structures and the body regions stripes extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer contacts the source regions. At least one elementary structure comprises at least a second zone adapted to allow the direct contact between the first metal layer and the underlying substrate portion arranged between two adjacent body regions stripes to perform the Schottky diode.

摘要翻译： 示出了包括形成在第一导电类型的半导体衬底上的MOS晶体管和肖特基二极管的集成器件。 该装置包括彼此相邻并平行的第二导电类型的多个体区条纹，放置在所述基底上的第一金属层和置于所述基底下的第二金属层。 该器件包括彼此平行的多个基本结构，每个基本结构包括第一区域，该第一区域设置有位于两个相邻体区条纹之间的衬底的一部分上的氧化硅层，叠加到氧化硅上的多晶硅层 层，放置在多晶硅层上方和周围的介电层。 一些体区条纹包括与基本结构的第一区相邻放置的第一导电类型的源区，以形成所述MOS晶体管的元件。 基本结构和体区条纹以横向方式纵向延伸，以在MOS晶体管的基本单元中形成沟道，并且第一金属层接触源极区。 至少一个基本结构包括至少第二区域，适于允许第一金属层与布置在两个相邻体区条纹之间的下面的基底部分之间的直接接触以执行肖特基二极管。

公开(公告)号：US20060183267A1

公开(公告)日：2006-08-17

申请号：US11236304

申请日：2005-09-27

申请人： Fabrizio Roccaforte ,  Vito Raineri ,  Francesco La Via ,  Mario Saggio

发明人： Fabrizio Roccaforte ,  Vito Raineri ,  Francesco La Via ,  Mario Saggio

IPC分类号： H01L21/00

CPC分类号： H01L21/0435 ,  H01L21/0415

摘要： A process realizes a Schottky contact on an epitaxial layer of a semiconductor substrate. The process includes depositing a conductive metallic layer on a surface of the epitaxial layer, with achievement of a interface region of conductive metallic layer/semiconductor. The process further comprises a ionic irradiation step directed towards the surface of the epitaxial layer for forming a modified intermediate layer of at least one surface portion of the epitaxial layer for making the electric behavior of the interface region substantially dependant on the contact between the conductive metallic layer and the obtained modified intermediate layer.

摘要翻译： 一种工艺在半导体衬底的外延层上实现肖特基接触。 该方法包括在外延层的表面上沉积导电金属层，实现导电金属层/半导体的界面区域。 该方法还包括指向外延层的表面的离子照射步骤，用于形成外延层的至少一个表面部分的改性中间层，以使界面区域的电性能基本上取决于导电金属 层和得到的改性中间层。

公开(公告)号：US06762112B2

公开(公告)日：2004-07-13

申请号：US10079925

申请日：2002-02-20

申请人： Vito Raineri ,  Mario Saggio

发明人： Vito Raineri ,  Mario Saggio

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/7602

摘要： A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.

摘要翻译： 在碳化硅层中形成隔离结构的方法包括在碳化硅层的第一和第二部分上沉积掩模层，以及通过掩模层形成开口以露出碳化硅层的第一部分。 离子被注入到碳化硅层的第一部分中。 加热碳化硅层以形成其上具有在碳化硅层的第一部分上的第一部分并且在碳化硅层的第二部分上具有第二部分的氧化物层。 蚀刻氧化物层的第一部分以在碳化硅层中形成隔离区。

公开(公告)号：US20080001223A1

公开(公告)日：2008-01-03

申请号：US11824169

申请日：2007-06-28

申请人： Mario Saggio ,  Domenico Murabito ,  Ferruccio Frisina

发明人： Mario Saggio ,  Domenico Murabito ,  Ferruccio Frisina

IPC分类号： H01L21/336 ,  H01L29/768

CPC分类号： H01L29/7811 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

摘要： An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region.

摘要翻译： 制造半导体功率器件的方法的一个实施例设想了以下步骤：提供由具有第一顶表面的半导体材料制成的本体; 在所述第一顶表面附近和所述主体的活动部分内部形成具有第一类型导电性的有源区; 并形成边缘终端结构。 边缘终端结构通过以下方式形成：具有第一类型的导电性和第一掺杂水平的环形区域，其设置在主体的外围边缘部分内并电连接到有源区域; 以及保护区，其具有高于第一掺杂级的第一类型的导电性和第二掺杂级，设置在第一顶表面附近并将有源区连接到环区。 该方法进一步设想了以下步骤：在第一顶表面上形成具有第一类型导电性的表面层，也在周边边缘部分形成与保护区域接触的表面层; 并且蚀刻表面层以便以这样的方式将其去除边缘部分，使得蚀刻终止于保护区域内。

公开(公告)号：US06841836B2

公开(公告)日：2005-01-11

申请号：US10738952

申请日：2003-12-16

申请人： Mario Saggio ,  Ferruccio Frisina

发明人： Mario Saggio ,  Ferruccio Frisina

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/72

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

摘要： An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor. The elementary structures and the body regions stripes extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer contacts the source regions. At least one elementary structure comprises at least a second zone adapted to allow the direct contact between the first metal layer and the underlying substrate portion arranged between two adjacent body regions stripes to perform the Schottky diode.

公开(公告)号：US06709955B2

公开(公告)日：2004-03-23

申请号：US09842841

申请日：2001-04-27

申请人： Mario Saggio ,  Vito Raineri ,  Umberto Stagnitti ,  Sebastiano Mugavero

发明人： Mario Saggio ,  Vito Raineri ,  Umberto Stagnitti ,  Sebastiano Mugavero

IPC分类号： H01L21322

CPC分类号： H01L21/3223 ,  Y10S257/913

摘要： A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.

摘要翻译： 一种制造电子器件的方法，整体地集成在半导体衬底中，所述半导体衬底具有与至少一个器件有源区相邻的至少一个非有源区，该方法包括至少一个注入惰性气体离子的步骤，随后进行热处理 通过惰性气体的蒸发在半导体中形成吸气剂微腔，其中注入步骤在半导体的非有源区域中进行。

公开(公告)号：US06404010B2

公开(公告)日：2002-06-11

申请号：US09860809

申请日：2001-05-17

申请人： Mario Saggio ,  Ferruccio Frisina ,  Angelo Magri'

发明人： Mario Saggio ,  Ferruccio Frisina ,  Angelo Magri'

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634

摘要： A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between the two body regions. The first semiconductor region is placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer. A plurality of second lightly doped semiconductor regions of the first conductivity type are placed under said at least two heavily doped body regions and under said first lightly doped semiconductor region of the first conductivity type, each region of said plurality of second lightly doped semiconductor regions of the first conductivity type being separated from the other by portions of said semiconductor layer of the second conductivity type.

摘要翻译： 描述了MOS技术功率器件，其包括多个基本有源单元和放置在形成基本有源单元的区域之间的所述功率器件的一部分。 功率器件的一部分包括形成在第二导电类型的半导体层中的第一导电类型的至少两个重掺杂体区域，第一导电类型的第一轻掺杂半导体区域横向放置在两者之间 身体区域。 第一半导体区域被放置在一连串厚的氧化硅层，多晶硅层和金属层之下。 第一导电类型的多个第二轻掺杂半导体区域被放置在所述至少两个重掺杂体区域的下方，并且在所述第一导电类型的所述第一轻掺杂半导体区域的下方，所述多个第二轻掺杂半导体区域的每个区域 所述第一导电类型通过所述第二导电类型的所述半导体层的一部分与另一个分离。

公开(公告)号：US20050118766A1

公开(公告)日：2005-06-02

申请号：US11023957

申请日：2004-12-28

申请人： Mario Saggio ,  Ferruccio Frisina

发明人： Mario Saggio ,  Ferruccio Frisina

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7806

摘要： An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor. The elementary structures and the body regions stripes extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer contacts the source regions. At least one elementary structure comprises at least a second zone adapted to allow the direct contact between the first metal layer and the underlying substrate portion arranged between two adjacent body regions stripes to perform the Schottky diode.

摘要翻译： 示出了包括形成在第一导电类型的半导体衬底上的MOS晶体管和肖特基二极管的集成器件。 该装置包括彼此相邻并平行的第二导电类型的多个体区条纹，放置在所述基底上的第一金属层和置于所述基底下的第二金属层。 该器件包括彼此平行的多个基本结构，每个基本结构包括第一区域，该第一区域设置有位于两个相邻体区条纹之间的衬底的一部分上的氧化硅层，叠加到氧化硅上的多晶硅层 层，放置在多晶硅层上方和周围的介电层。 一些体区条纹包括与基本结构的第一区相邻放置的第一导电类型的源区，以形成所述MOS晶体管的元件。 基本结构和体区条纹以横向方式纵向延伸，以在MOS晶体管的基本单元中形成沟道，并且第一金属层接触源极区。 至少一个基本结构包括至少第二区域，其适于允许第一金属层与布置在两个相邻体区条纹之间的下面的衬底部分之间的直接接触以执行肖特基二极管。