公开(公告)号：US07247877B2

公开(公告)日：2007-07-24

申请号：US10711083

申请日：2004-08-20

申请人： Mark C. Hakey ,  Mark E. Masters ,  Leah M. P. Pastel ,  David P. Vallett

发明人： Mark C. Hakey ,  Mark E. Masters ,  Leah M. P. Pastel ,  David P. Vallett

IPC分类号： H01L31/072 ,  H01L23/48

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G01R31/2884 ,  H01L27/088 ,  H01L27/286 ,  H01L29/0673 ,  H01L29/78 ,  H01L51/0048 ,  H01L51/0512 ,  Y10S977/761 ,  Y10S977/762 ,  Y10S977/765

摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.

摘要翻译： 一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。 此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。 此外，CNT FET适用于检测集成电路内的故障电路。

公开(公告)号：US07089138B1

公开(公告)日：2006-08-08

申请号：US10906590

申请日：2005-02-25

申请人： Pierre J. Bouchard ,  Mark C. Hakey ,  Mark E. Masters ,  Leah M. P. Pastel ,  James A. Slinkman ,  David P. Vallett

发明人： Pierre J. Bouchard ,  Mark C. Hakey ,  Mark E. Masters ,  Leah M. P. Pastel ,  James A. Slinkman ,  David P. Vallett

IPC分类号： G06F11/00

CPC分类号： G01R31/2856 ,  G01R31/2831 ,  G01R31/318511 ,  G01R31/3187

摘要： A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.

摘要翻译： 一种在其制造期间测试集成电路的诊断系统和方法。 诊断系统具有至少一个具有与其相关联的电特征的集成电路芯片; 牺牲电路，其与集成电路芯片相邻并且具有与其相关联的已知电气签名和故意错误设计的电路; 以及比较器，用于将集成电路芯片的电特征与牺牲电路的已知电特征进行比较，其中集成电路芯片的电特征中与牺牲电路的已知电气签名的匹配指示集成电路 芯片设计错误。 诊断系统还包括具有多个集成电路芯片的半导体晶片和将一个集成电路芯片与另一个集成电路芯片分离的切口区域。 错误设计的集成电路芯片具有异常功能的电路。

公开(公告)号：US07484423B2

公开(公告)日：2009-02-03

申请号：US11696370

申请日：2007-04-04

申请人： Mark C. Hakey ,  Mark E. Masters ,  Leah M. P. Pastel ,  David P. Vallett

发明人： Mark C. Hakey ,  Mark E. Masters ,  Leah M. P. Pastel ,  David P. Vallett

IPC分类号： G01B7/16 ,  G01L1/00 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G01R31/2884 ,  H01L27/088 ,  H01L27/286 ,  H01L29/0673 ,  H01L29/78 ,  H01L51/0048 ,  H01L51/0512 ,  Y10S977/761 ,  Y10S977/762 ,  Y10S977/765

摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.

摘要翻译： 一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。 此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。 此外，CNT FET适用于检测集成电路内的故障电路。

公开(公告)号：US08039334B2

公开(公告)日：2011-10-18

申请号：US12902944

申请日：2010-10-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/8234

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US20110027951A1

公开(公告)日：2011-02-03

申请号：US12902944

申请日：2010-10-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/8234

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US07535016B2

公开(公告)日：2009-05-19

申请号：US10906016

申请日：2005-01-31

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters ,  Peter H. Mitchell

IPC分类号： H01L29/15 ,  H01L51/30

CPC分类号： H01L27/0688 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/0705 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/938

摘要： A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor.

摘要翻译： 提供一种混合半导体结构，其包括水平半导体器件和垂直碳纳米管晶体管，其中垂直碳纳米管晶体管和水平半导体器件具有至少一个共享节点。 至少一个共享节点可以包括例如FET的漏极，源极或栅极电极，或双极晶体管的发射极，集电极或基极。

公开(公告)号：US07838943B2

公开(公告)日：2010-11-23

申请号：US11161146

申请日：2005-07-25

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/70

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US08284017B2

公开(公告)日：2012-10-09

申请号：US13283328

申请日：2011-10-27

申请人： Mark C. Hakey ,  Stephen E. Luce ,  James S. Nakos

发明人： Mark C. Hakey ,  Stephen E. Luce ,  James S. Nakos

IPC分类号： H01C1/012

CPC分类号： H01C3/12 ,  G06F17/5045

摘要： A design structure including a pair of substantially parallel resistor material lengths separated by a first dielectric are disclosed. The resistor material lengths have a sub-lithographic dimension and may be spacer shaped.

摘要翻译： 公开了一种包括由第一电介质隔开的一对基本平行的电阻材料长度的设计结构。 电阻材料长度具有亚光刻尺寸并且可以是间隔件形状。

公开(公告)号：US08044764B2

公开(公告)日：2011-10-25

申请号：US12046647

申请日：2008-03-12

申请人： Mark C. Hakey ,  Stephen E. Luce ,  James S. Nakos

发明人： Mark C. Hakey ,  Stephen E. Luce ,  James S. Nakos

IPC分类号： H01C1/012

CPC分类号： H01C3/12 ,  G06F17/5045

摘要： A resistor and design structure including at least one resistor material length in a dielectric, each of the least one resistor material length having a sub-lithographic width are disclosed.

摘要翻译： 公开了一种电阻器和设计结构，其包括在电介质中的至少一个电阻器材料长度，所述至少一个电阻器材料长度中的每一个具有亚光刻宽度。

公开(公告)号：US08004024B2

公开(公告)日：2011-08-23

申请号：US12348404

申请日：2009-01-05

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/423 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78621 ,  Y10S977/742 ,  Y10S977/847

摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

摘要翻译： 晶体管。 晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。