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1.发明授权Method and apparatus for control of critical dimension using feedback etch control 有权使用反馈蚀刻控制来控制临界尺寸的方法和装置公开(公告)号：US06245581B1
公开(公告)日：2001-06-12
申请号：US09552491
申请日：2000-04-19
IPC分类号： H01L2100
CPC分类号： H01L21/67276 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for a method and an apparatus for controlling critical dimensions. At least one run of semiconductor devices is processed. A critical dimension measurement is performed upon at least one of the processed semiconductor device. An analysis of the critical dimension measurement is performed. A secondary process upon the semiconductor device in response to the critical dimension analysis is performed.
摘要翻译： 本发明提供了一种用于控制关键尺寸的方法和装置。 至少运行一半的半导体器件被处理。 对所处理的半导体器件中的至少一个进行临界尺寸测量。 执行关键尺寸测量的分析。 执行响应于临界尺寸分析的半导体器件上的二次工艺。
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公开(公告)号：US06734088B1
公开(公告)日：2004-05-11
申请号：US09661536
申请日：2000-09-14
IPC分类号： H01L213205
CPC分类号： H01L22/20 , H01L21/28035
摘要： The present invention is directed to a method of controlling an etching process used to form a gate electrode on a semiconductor device. In one embodiment, the method comprises forming a layer of silicon dioxide above a semiconducting substrate, and forming a layer of polysilicon above the layer of silicon dioxide. The method further comprises sensing a thickness of the layer of polysilicon and adjusting, based upon the sensed thickness of said layer of polysilicon, at least one parameter of an etching process to be performed on said layer of polysilicon to define a gate electrode of a transistor, said etching process comprised of at least a timed etch process and an endpoint etch process.
摘要翻译： 本发明涉及一种控制用于在半导体器件上形成栅电极的蚀刻工艺的方法。 在一个实施例中，该方法包括在半导体衬底上形成二氧化硅层，并在二氧化硅层之上形成多晶硅层。 该方法还包括感测多晶硅层的厚度，并且基于感测到的所述多晶硅层的厚度调整要在所述多晶硅层上执行的蚀刻工艺的至少一个参数，以限定晶体管的栅电极 所述蚀刻工艺至少包括定时蚀刻工艺和端蚀刻工艺。
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3.发明授权Dry isotropic removal of inorganic anti-reflective coating after poly gate etching 有权多栅极蚀刻后无机抗反射涂层的干均匀去除公开(公告)号：US06555397B1
公开(公告)日：2003-04-29
申请号：US09660723
申请日：2000-09-13
IPC分类号： H01L2128
CPC分类号： H01L21/28123 , Y10S438/952
摘要： Various methods of fabricating a conductor structure are provided. In one aspect, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon film are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching. Use of isotropic etching for anti-reflective coating removal eliminates thermal shock associated with heated acid bath anti-reflective coating removal.
摘要翻译： 提供制造导体结构的各种方法。 一方面，提供了在第一工件上制造导体结构的方法。 在第一工件上形成硅膜。 在硅膜上形成抗反射涂层。 掩模形成在防反射涂层的第一部分上，而其第二部分未被掩蔽。 抗反射涂层和硅膜的第二部分被蚀刻。 除去掩模，并通过各向同性等离子体蚀刻除去抗反射涂层。 使用各向同性蚀刻进行抗反射涂层去除消除了与加热的酸浴反射涂层去除相关的热冲击。
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公开(公告)号：US5370923A
公开(公告)日：1994-12-06
申请号：US23078
申请日：1993-02-26
申请人： Howard S. Goad , Derick J. Wristers , James H. Hussey, Jr. , Michael A. Hillis , William C. Chapman
发明人： Howard S. Goad , Derick J. Wristers , James H. Hussey, Jr. , Michael A. Hillis , William C. Chapman
IPC分类号： G03F7/20 , H01L21/66 , H01L23/544 , B32B9/00
CPC分类号： G03F7/70658 , H01L22/34 , H01L22/12 , Y10S428/901 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926
摘要： A photolithography test structure is provided for measuring the amount of notching associated with photolithography processing. The test structure includes a curved insulating structure placed in close spaced proximity with a conductive, interconnect structure. A pair of conductive pads are deposited at opposite ends of the interconnect structure for measuring the resistance through the interconnect. Depending upon the amount of notching associated with the interconnect, resistance readings will vary. Test areas containing notched interconnect can be compared with controlled areas specifically designed not to have notching in order to determine relative changes in resistance, and to correlate that resistance with notching magnitude. The insulating structure, interconnect structure and conductive pads are processed upon the same substrate material containing the resulting product requiring testing.
摘要翻译： 提供光刻测试结构用于测量与光刻处理相关的开槽量。 测试结构包括一个弯曲的绝缘结构，它与导电互连结构紧密隔开。 一对导电焊盘沉积在互连结构的相对端，用于通过互连测量电阻。 根据与互连相关的开槽量，电阻读数会有所不同。 可以将包含切口互连的测试区域与专门设计为不具有开槽的控制区域进行比较，以确定电阻的相对变化，并将该电阻与开槽幅度相关联。 绝缘结构，互连结构和导电焊盘在包含所需产品需要测试的相同基板材料上进行加工。
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公开(公告)号：US06728591B1
公开(公告)日：2004-04-27
申请号：US09920098
申请日：2001-08-01
IPC分类号： G06F1900
CPC分类号： H01L21/67276 , G05B2219/32179 , G05B2219/45031 , H01L21/67253 , Y02P90/22
摘要： A method and an apparatus are provided for performing run-to-run control of trench profiles. At least one semiconductor wafer is processed. A trench metrology data from the processed semiconductor wafer is acquired. Data relating to at least one process chamber characteristic is acquired while processing the semiconductor wafer. A chamber characteristic adjustment process is performed in response to the trench metrology data and the data relating to the processing chamber characteristic. A feedback adjustment of the processing chamber characteristic is performed in response to the chamber characteristic adjustment process.
摘要翻译： 提供了一种方法和装置，用于对沟槽轮廓执行跑步运行控制。 至少一个半导体晶片被处理。 获得来自处理后的半导体晶片的沟槽测量数据。 在处理半导体晶片时获取与至少一个处理室特性有关的数据。 响应于沟槽测量数据和与处理室特性相关的数据执行室特性调整处理。 响应于腔室特性调整过程执行处理室特性的反馈调整。
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公开(公告)号：US5472774A
公开(公告)日：1995-12-05
申请号：US292873
申请日：1994-08-19
申请人： Howard S. Goad , Derick J. Wristers , James H. Hussey, Jr. , Michael A. Hillis , William C. Chapman
发明人： Howard S. Goad , Derick J. Wristers , James H. Hussey, Jr. , Michael A. Hillis , William C. Chapman
IPC分类号： G03F7/20 , H01L21/66 , H01L23/544 , B32B9/00
CPC分类号： G03F7/70658 , H01L22/34 , H01L22/12 , Y10S428/901 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926
摘要： A photolithography test structure is provided for measuring the amount of notching associated with photolithography processing. The test structure includes a curved insulating structure placed in close spaced proximity with a conductive, interconnect structure. A pair of conductive pads are deposited at opposite ends of the interconnect structure for measuring the resistance through the interconnect. Depending upon the amount of notching associated with the interconnect, resistance readings will vary. Test areas containing notched interconnect can be compared with controlled areas specifically designed not to have notching in order to determine relative changes in resistance, and to correlate that resistance with notching magnitude. The insulating structure, interconnect structure and conductive pads are processed upon the same substrate material containing the resulting product requiring testing.
摘要翻译： 提供光刻测试结构用于测量与光刻处理相关的开槽量。 测试结构包括一个弯曲的绝缘结构，它与导电互连结构紧密隔开。 一对导电焊盘沉积在互连结构的相对端，用于通过互连测量电阻。 根据与互连相关的开槽量，电阻读数会有所不同。 可以将包含切口互连的测试区域与专门设计为不具有开槽的控制区域进行比较，以确定电阻的相对变化，并将该电阻与开槽幅度相关联。 绝缘结构，互连结构和导电焊盘在包含所需产品需要测试的相同基板材料上进行加工。
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