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1.发明授权Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions 失效用于形成具有特定尺寸的栅极侧壁间隔物的半导体装置的方法公开(公告)号：US07279386B2
公开(公告)日：2007-10-09
申请号：US11002586
申请日：2004-12-03
IPC分类号： H01L21/335
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/32139 , H01L29/66628 , H01L29/66659
摘要： A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
摘要翻译： 在多晶硅栅电极上形成特定尺寸的间隔物的方法在选择性外延生长期间保护多晶硅栅电极的侧壁。 无论是不对称的还是对称的，通过在限定多晶硅栅电极图案和图案中使用相同的特定曝光工具（例如193nm波长步长和扫描曝光工具）和相同的图案掩模版来精确限定 间隔件，同时采用紧密对准规格。
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公开(公告)号：US07144785B2
公开(公告)日：2006-12-05
申请号：US10976869
申请日：2004-11-01
IPC分类号： H01L21/336
CPC分类号： H01L21/76224
摘要： A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.
摘要翻译： 具有浅沟槽隔离（STI）结构的应变硅半导体装置具有在硅锗（SiGe）层上形成的应变硅（Si）层。 沟槽穿过Si层延伸到SiGe层中，并且采用覆盖SiGe层中的沟槽内的整个侧壁的侧壁间隔物。 在STI填充，抛光和氮化物剥离工艺步骤之后，可以进行进一步处理，而不用关心SiGe层暴露于硅化物形成过程。
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3.发明授权Method of forming a semiconductor arrangement with reduced field-to active step height 失效形成具有减小的场到活动台阶高度的半导体装置的方法公开(公告)号：US07223698B1
公开(公告)日：2007-05-29
申请号：US11053910
申请日：2005-02-10
申请人： Douglas J. Bonser , Srikanteswara Dakshina-Murthy , Mark C. Kelling , John G. Pellerin , Johannes F. Groschopf , Edward Asuka Nomura
发明人： Douglas J. Bonser , Srikanteswara Dakshina-Murthy , Mark C. Kelling , John G. Pellerin , Johannes F. Groschopf , Edward Asuka Nomura
IPC分类号： H01L21/311
CPC分类号： H01L21/76232
摘要： A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.
摘要翻译： 在硅衬底中形成浅沟槽隔离（STI）区域的方法产生在硅衬底的顶表面上方延伸的STI区域。 在基板上形成平坦化介质层，并在场氧化物区域上方延伸。 平面化电介质层通过化学机械抛光或覆盖层回蚀除去，例如，以及在衬底的顶表面和活性区上延伸的场氧化物区域的那些部分。 从而消除或显着降低台阶高度。
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4.发明申请Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions 失效用于形成具有特定尺寸的栅极侧壁间隔物的半导体装置的方法公开(公告)号：US20060121711A1
公开(公告)日：2006-06-08
申请号：US11002586
申请日：2004-12-03
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/32139 , H01L29/66628 , H01L29/66659
摘要： A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
摘要翻译： 在多晶硅栅电极上形成特定尺寸的间隔物的方法在选择性外延生长期间保护多晶硅栅电极的侧壁。 无论是不对称的还是对称的，通过在限定多晶硅栅电极图案和图案中使用相同的特定曝光工具（例如193nm波长步长和扫描曝光工具）和相同的图案掩模版来精确限定 间隔件，同时采用紧密对准规格。
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公开(公告)号：US20060094205A1
公开(公告)日：2006-05-04
申请号：US10976869
申请日：2004-11-01
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.
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公开(公告)号：US20050020019A1
公开(公告)日：2005-01-27
申请号：US10922093
申请日：2004-08-19
申请人： Douglas Bonser , Marina Plat , Chih Yang , Scott Bell , Srikanteswara Dakshina-Murthy , Philip Fisher , Christopher Lyons
发明人： Douglas Bonser , Marina Plat , Chih Yang , Scott Bell , Srikanteswara Dakshina-Murthy , Philip Fisher , Christopher Lyons
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L21/3205
CPC分类号： H01L29/66477 , H01L21/28123 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
摘要翻译： 为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。 然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。 所得到的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。
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公开(公告)号：US07105399B1
公开(公告)日：2006-09-12
申请号：US11004951
申请日：2004-12-07
IPC分类号： H01L21/302 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84
摘要： Gate electrodes with selectively tuned channel thicknesses are formed by selective epitaxial growth. Embodiments include forming shallow trench isolation regions in an SOI substrate, selectively removing the nitride stop layer and pad oxide layer in an exposed particular active region, and implementing selective epitaxial growth to increase the thickness of the semiconductor layer in the particular active region. Subsequently, the remaining nitride stop and pad oxide layers in other active regions are removed, gate dielectric layers formed, as by thermal oxidation, and the transistors completed.
摘要翻译： 通过选择性外延生长形成具有选择性调谐的沟道厚度的栅极。 实施例包括在SOI衬底中形成浅沟槽隔离区域，选择性地去除暴露的特定有源区域中的氮化物阻挡层和衬垫氧化物层，以及实现选择性外延生长以增加特定有源区域中的半导体层的厚度。 随后，去除其它有源区中剩余的氮化物阻挡层和焊盘氧化物层，如通过热氧化形成栅介电层，并完成晶体管。
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8.发明申请Method of reducing STI divot formation during semiconductor device fabrication 有权在半导体器件制造期间减少STI纹路形成的方法公开(公告)号：US20050196928A1
公开(公告)日：2005-09-08
申请号：US10791759
申请日：2004-03-04
申请人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
发明人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.
摘要翻译： 通过使用非常薄的氮化物抛光停止层例如不厚于400来消除或显着降低STI纹线形成。 非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。
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9.发明授权公开(公告)号：US08547521B1
公开(公告)日：2013-10-01
申请号：US11000653
申请日：2004-12-01
CPC分类号： G03F7/70891 , G03F7/70341
摘要： The subject invention provides systems and methods that monitor and/or control turbulence of an immersion medium. The systems and methods relate to computer controlled techniques that reduce effects of immersion medium flow due to a liquid temperature gradient. According to an aspect of the subject invention, a number of temperature measurements of the immersion medium are obtained, and the temperature measurements are utilized to generate a gradient map of the immersion medium. By way of illustration, the temperature measurements can be made via wireless temperature sensors. The gradient map can be utilized to understand the stability of the immersion medium. According to an aspect of the subject invention, instability identified with the gradient map can be mitigated.
摘要翻译： 本发明提供了监测和/或控制浸没介质的湍流的系统和方法。 这些系统和方法涉及由于液体温度梯度而降低浸没介质流动影响的计算机控制技术。 根据本发明的一个方面，获得浸渍介质的多个温度测量值，并利用温度测量值来产生浸渍介质的梯度图。 作为说明，可以通过无线温度传感器进行温度测量。 梯度图可用于了解浸没介质的稳定性。 根据本发明的一个方面，可以减轻用梯度图识别的不稳定性。
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公开(公告)号：US07737021B1
公开(公告)日：2010-06-15
申请号：US10261613
申请日：2002-09-30
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
摘要翻译： 本发明涉及一种形成半导体器件的方法。 在一个说明性实施例中，该方法包括在形成在电介质材料层上方的光致抗蚀剂层中限定具有第一尺寸的光致抗蚀剂特征。 该方法还包括减小光致抗蚀剂特征的第一尺寸以产生减小尺寸的光致抗蚀剂特征，在减小尺寸的光致抗蚀剂特征下的电介质材料层中形成开口，以及在电介质材料层中的开口中形成导电材料 。
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