摘要:
A methodology has been discovered for transforming garbage collection-dependent algorithms, shared object implementations and/or concurrent software mechanisms into a form that does not presume the existence of an independent, or execution environment provided, garbage collector. Algorithms, shared object implementations and/or mechanisms designed or transformed using techniques described herein provide explicit reclamation of storage using lock-free pointer operations. Transformations can be applied to lock-free algorithms and shared object implementations and preserve lock-freedom of such algorithms and implementations. As a result, existing and future lock-free algorithms and shared object implementations that depend on a garbage-collected execution environment can be exploited in environments that do not provide garbage collection. Furthermore, algorithms and shared object implementations that employ explicit reclamation of storage using lock-free pointer operations such as described herein may be employed in the implementation of a garbage collector itself.
摘要:
In some embodiments, a Hat Trick deque requires only a single DCAS for most pushes and pops. The left and right ends do not interfere with each other until there is one or fewer items in the queue, and then a DCAS adjudicates between competing pops. By choosing a granularity greater than a single node, the user can amortize the costs of adding additional storage over multiple push (and pop) operations that employ the added storage. A suitable removal strategy can provide similar amortization advantages. The technique of leaving spare nodes linked in the structure allows an indefinite number of pushes and pops at a given deque end to proceed without the need to invoke memory allocation or reclamation so long as the difference between the number of pushes and the number of pops remains within given bounds. Both garbage collection dependent and explicit reclamation implementations are described.
摘要:
One embodiment of the present invention provides a system that facilitates performing operations on a lock-free double-ended queue (deque). This deque is implemented as a doubly-linked list of nodes formed into a ring, so that node pointers in one direction form an inner ring, and node pointers in the other direction form an outer ring. The deque has an inner hat, which points to a node next to the last occupied node along the inner ring, and an outer hat, which points to a node next to the last occupied node along the outer ring. The system uses a double compare-and-swap (DCAS) operation while performing pop and push operations onto either end of the deque, as well as growing and shrinking operations to change the number of nodes that are in the ring used by the deque.
摘要:
A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact. The result generator circuit may ignore the encoded floating point statuses of the plurality of floating point operands when comparing just the magnitudes of the plurality of floating point operands.
摘要:
In computer systems which do not inherently distinguish between references and primitive values within a program stack a method and apparatus to assist exact garbage collection techniques utilizes a stack tag cache which operates in conjunction with a program stack and supplies a tag item for every entry in the process stack. The value of a tag item indicates whether the stack entry is either a reference to another memory location or a primitive value, i.e. integer or floating point number. The arrangements and values of the tag items are correlated with changes to the program stack. The stack tag cache includes facilities for swapping the contents of the cache in the event of a trap or context switch, as well as means for redundantly verifying the tag value with intended instruction operand types.
摘要:
A vehicle body lowering system for installation in a motor vehicle having a wheeled carriage, a cargo/passenger compartment body, a door in the passenger compartment body for cargo loading and unloading or passenger embarking and debarking, and a spring suspension for the buoyant support of the body above the carriage between a lower position and an upper position. The components of the vehicle body lowering system include a hydraulic cylinder mounted within the body, a power source, a manually actuated control for energizing and deenergizing the power source, and an interconnection extending through the body between the cylinder and the carriage. The interconnection is characterized by an operative condition at which the body is in the lower position under the control of the power source, and an inoperative condition at which the body is freely subject to the buoyant support of the spring suspension.
摘要:
The vehicle body lowering system of the present invention is installed in a motor vehicle having a wheeled carriage, a cargo/passenger compartment body, a door in the passenger compartment body for cargo loading and unloading or passenger embarking and debarking, and a spring suspension for the buoyant support of the body above the carriage between a lower position and an upper position. The components of the vehicle body lowering system include a drive for forcing the body into the lower position, where the drive comprises a power source and an interconnection between the body and the carriage, and a manually actuated control for energizing and deenergizing the power source. The interconnection is characterized by an operative condition at which the body is in the lower position under the control of the power source, and an inoperative condition at which the body is freely subject to the buoyant support of the spring suspension. The interconnection has at least one coupling to the body and at least one coupling to the carriage.
摘要:
A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.
摘要:
A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction. The floating point total order comparator circuit may recognize several predetermined operand formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact.