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    Method and apparatus for exchanging data, status, and commands over an hierarchical serial bus assembly using communication packets
    3.
    发明授权
    Method and apparatus for exchanging data, status, and commands over an hierarchical serial bus assembly using communication packets 失效
    用于使用通信分组通过分层串行总线组件交换数据，状态和命令的方法和装置

    公开(公告)号：US5694555A

    公开(公告)日：1997-12-02

    申请号：US619863

    申请日：1996-03-19

    申请人： Jeff Charles Morriss ,  Shaun Knoll ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Ajay V. Bhatt ,  Sudarshan Bala Cadambi

    发明人： Jeff Charles Morriss ,  Shaun Knoll ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Ajay V. Bhatt ,  Sudarshan Bala Cadambi

    IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

    CPC分类号： H04L12/40058 ,  G06F13/385 ,  G06F13/4291 ,  H04L12/40071 ,  H04L12/40117 ,  H04L12/40123

    摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

    摘要翻译： 电路和互补逻辑被提供给总线控制器，多个1：n总线信号分配器，以及用于在互连到分层总线组件的总线代理之间进行数据通信事务的分层总线组件的多个总线接口。 分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 串行总线元件的这些电路和互补逻辑实现了许多元件分组和多个事务处理协议，采用事务流控制的主/从模型。 数据通信事务使用元素数据包进行，并根据事务协议进行。 在一些实施例中，串行总线元件的这些电路和互补逻辑也用于在串行总线元件之间进行连接管理事务。 连接管理事务以与数据通信事务相同的方式进行。

    M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions
    4.
    发明授权
    M&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functions 失效
    用于动态生成和维护用于轮询等时和异步功能的基于帧的轮询时间表的并购，其保证等时功能的延迟和带宽

    公开(公告)号：US5742847A

    公开(公告)日：1998-04-21

    申请号：US331727

    申请日：1994-10-31

    申请人： Shaun Knoll ,  Jeff Charles Morriss ,  Ajay V. Bhatt ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Sudarshan Bala Cadambi

    发明人： Shaun Knoll ,  Jeff Charles Morriss ,  Ajay V. Bhatt ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Sudarshan Bala Cadambi

    IPC分类号： G06F13/10 ,  G06F13/22 ,  G06F13/40 ,  H04L12/40 ,  H04L12/64 ,  G06F13/14 ,  G06F13/20

    CPC分类号： H04L12/40058 ,  G06F13/10 ,  G06F13/22 ,  G06F13/4022 ,  H04L12/40065

    摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

    摘要翻译： 电路和互补逻辑提供给总线控制器，多个1：n总线信号分配器，以及用于总线控制器的分级串行总线组件的多个总线接口，用于动态生成并维护基于帧的轮询时间表，以轮询 总线代理连接到串行总线组件和串行总线元件本身的功能。 分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 串行总线元件的这些电路和互补逻辑支持总线控制器收集各种关键操作特性。 提供给总线控制器的电路和逻辑依次产生基于帧的轮询调度，这些收集的关键操作特性，保证等时外设的同步功能的延迟和带宽。 在某些实施例中，响应于串行总线元件的实时连接/分离，提供给总线控制器的电路和逻辑进一步适应实时地基于其基于帧的轮询调度。

    M&A for exchanging date, status and commands over an hierarchical serial bus assembly using communication packets
    5.
    发明授权
    M&A for exchanging date, status and commands over an hierarchical serial bus assembly using communication packets 失效
    通过分层串行总线组合使用通信包交换日期，状态和命令的并购

    公开(公告)号：US5909556A

    公开(公告)日：1999-06-01

    申请号：US980507

    申请日：1997-12-01

    申请人： Jeff Charles Morriss ,  Shaun Knoll ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Ajay V. Bhatt ,  Sudarshan Bala Cadambi

    发明人： Jeff Charles Morriss ,  Shaun Knoll ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Ajay V. Bhatt ,  Sudarshan Bala Cadambi

    IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

    CPC分类号： H04L12/40058 ,  G06F13/385 ,  G06F13/4291 ,  H04L12/40071 ,  H04L12/40117 ,  H04L12/40123

    摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

    摘要翻译： 电路和互补逻辑被提供给总线控制器，多个1：n总线信号分配器，以及用于在互连到分层总线组件的总线代理之间进行数据通信事务的分层总线组件的多个总线接口。 分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 串行总线元件的这些电路和互补逻辑实现了许多元件分组和多个事务处理协议，采用事务流控制的主/从模型。 数据通信事务使用元素数据包进行，并根据事务协议进行。 在一些实施例中，串行总线元件的这些电路和互补逻辑也用于在串行总线元件之间进行连接管理事务。 连接管理事务以与数据通信事务相同的方式进行。

    Method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link
    6.
    发明授权
    Method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link 失效
    满足多速度点对点链路调试和测试的依从性的方法和装置

    公开(公告)号：US07633877B2

    公开(公告)日：2009-12-15

    申请号：US11283303

    申请日：2005-11-18

    申请人： Debendra Das Sharma ,  Ajay V. Bhatt ,  David S. Dunning

    发明人： Debendra Das Sharma ,  Ajay V. Bhatt ,  David S. Dunning

    IPC分类号： H04L12/26

    CPC分类号： H04L43/50

    摘要： A method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link. In one embodiment, the method includes the selection of a compliance speed for a point-to-point link from at least two link frequencies supported by the point-to-point link. Once the compliance speed is selected for the point-to-point link, the point-to-point link is caused to enter a compliance testing mode. During compliance testing mode, a controller of the point-to-point link sets a compliance speed of the point-to-point link to the selected compliance speed. Once a compliance speed is set, a transmitter of the point-to-point link transmits a compliance pattern at the selected compliance speed. In one embodiment, the transmission of the compliance pattern at the selected compliance speed is used to generate a worst case eye diagram to determine compliance of the point-to-point link to a link specification. Other embodiments are described and claimed.

    摘要翻译： 一种用于满足调试和测试多速点对点链路的符合性的方法和装置。 在一个实施例中，该方法包括从点对点链路所支持的至少两个链路频率中选择点对点链路的遵从速度。 一旦为点对点链路选择了合规性速度，点对点链路便进入合规性测试模式。 在合规测试模式期间，点对点链路的控制器将点对点链路的合规速度设置为所选择的合规速度。 一旦达到合规速度，点对点链路的发射机就以所选择的合规速度传输合规模式。 在一个实施例中，以所选择的合规速度传输合规性模式用于生成最坏情况的眼图，以确定点对点链路对链路规范的顺从性。 描述和要求保护其他实施例。