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公开(公告)号：US08587602B2
公开(公告)日：2013-11-19
申请号：US12857280
申请日：2010-08-16
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2210/36
摘要： Systems and associated methods for processing textures in a graphical processing unit (GPU) are disclosed. Textures may be managed on a per region (e.g., tile) basis, which allows efficient use of texture memory. Moreover, very large textures may be used. Techniques provide for both texture streaming, as well as sparse textures. A GPU texture unit may be used to intelligently clamp LOD based on a shader specified value. The texture unit may provide feedback to the shader to allow the shader to react conditionally based on whether clamping was used, etc. Per region (e.g., per-tile) independent mipmap stacks may be used to allow very large textures.
摘要翻译： 公开了用于在图形处理单元（GPU）中处理纹理的系统和相关方法。 可以在每个区域（例如，瓦片）的基础上管理纹理，这允许纹理存储器的有效使用。 此外，可以使用非常大的纹理。 技术提供纹理流式传输以及稀疏纹理。 可以使用GPU纹理单元基于着色器指定值来智能地夹紧LOD。 纹理单元可以向着色器提供反馈以允许着色器基于是否使用夹紧等来有条件地进行反应。每个区域（例如，每个图块）独立的mipmap堆栈可以用于允许非常大的纹理。
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公开(公告)号：US20120038657A1
公开(公告)日：2012-02-16
申请号：US12857280
申请日：2010-08-16
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2210/36
摘要： Systems and associated methods for processing textures in a graphical processing unit (GPU) are disclosed. Textures may be managed on a per region (e.g., tile) basis, which allows efficient use of texture memory. Moreover, very large textures may be used. Techniques provide for both texture streaming, as well as sparse textures. A GPU texture unit may be used to intelligently clamp LOD based on a shader specified value. The texture unit may provide feedback to the shader to allow the shader to react conditionally based on whether clamping was used, etc. Per region (e.g., per-tile) independent mipmap stacks may be used to allow very large textures.
摘要翻译： 公开了用于在图形处理单元（GPU）中处理纹理的系统和相关方法。 可以在每个区域（例如，瓦片）的基础上管理纹理，这允许纹理存储器的有效使用。 此外，可以使用非常大的纹理。 技术提供纹理流式传输以及稀疏纹理。 可以使用GPU纹理单元基于着色器指定值来智能地夹紧LOD。 纹理单元可以向着色器提供反馈以允许着色器基于是否使用夹紧等来有条件地进行反应。每个区域（例如，每个图块）独立的mipmap堆栈可以用于允许非常大的纹理。
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3.发明申请公开(公告)号：US20120113118A1
公开(公告)日：2012-05-10
申请号：US13286054
申请日：2011-10-31
IPC分类号： G06T15/80
CPC分类号： G06T1/60 , G06T15/005
摘要： Utilizing intermediate target(s) in connection with computer graphics in a computer system is provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.
摘要翻译： 提供了与计算机系统中的计算机图形相关联的中间目标。 在各种实施例中，视频存储器中的中间存储器缓冲器被提供并用于允许来自图形API的序列化程序支持超过单个程序的程序着色器的指令限制的算法。 中间缓冲器也可以允许在用于其它目的的程序之间共享数据，并且是原子上可访问的。 缓冲器的大小可以相对于图形数据变化地设定为分辨率的变化。 在这方面，单个程序产生中间数据，然后可以通过相同程序和/或任何数量的其他程序的扩展来使用和重新使用任何次数的可能的期望，从而实现相当大的灵活性， 遮蔽程序的复杂性，同时保持现代图形芯片的速度。
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4.发明申请METHOD AND SYSTEM FOR DEFINING AND CONTROLLING ALGORITHMIC ELEMENTS IN A GRAPHICS DISPLAY SYSTEM 有权用于在图形显示系统中定义和控制算法元素的方法和系统公开(公告)号：US20100039430A1
公开(公告)日：2010-02-18
申请号：US12604102
申请日：2009-10-22
申请人： Charles N. Boyd , Michael A. Toelle
发明人： Charles N. Boyd , Michael A. Toelle
IPC分类号： G06T15/50
CPC分类号： G06T15/005
摘要： An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.
摘要翻译： 提供了一种能够实现3D芯片的可编程性的API，其中由开发者编写的编程或算法元素可以被下载到芯片，从而对芯片进行编程以执行这些算法。 开发人员将可下载的例程写入3D图形芯片。 还提供了一组与已经为开发人员编程的API相关联的算法元素，可以下载到可编程芯片以提高性能。 因此，开发人员可以将预先存在的API对象下载到3D图形芯片。 开发人员坚持使用特定格式来打包一个由3D图形芯片实现的算法元素或指令集。 开发人员通过参考3D图形芯片了解的“令牌”列表将指令集打包成数组。 这个数组依次被正确地映射到3D图形芯片，用于由3D图形芯片实现算法元素。
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5.发明授权公开(公告)号：US07564460B2
公开(公告)日：2009-07-21
申请号：US10196864
申请日：2002-07-16
IPC分类号： G06F15/80
CPC分类号： G06T1/60 , G06T15/005
摘要： Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system are provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modem graphics chips.
摘要翻译： 提供了一种在计算机系统中利用与计算机图形相关的中间目标的系统和方法。 在各种实施例中，视频存储器中的中间存储器缓冲器被提供并用于允许来自图形API的序列化程序支持超过单个程序的程序着色器的指令限制的算法。 中间缓冲器也可以允许在用于其它目的的程序之间共享数据，并且是原子上可访问的。 缓冲器的大小，即存储在中间目标中的数据量可以相对于图形数据可变地设置为分辨率的变化量。 在这方面，单个程序产生中间数据，然后可以通过相同程序和/或任何数量的其他程序的扩展来使用和重新使用任何次数的可能的期望，从而实现相当大的灵活性， 遮蔽程序的复杂性，同时保持调制解调器图形芯片的速度。
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公开(公告)号：US07064762B2
公开(公告)日：2006-06-20
申请号：US10979461
申请日：2004-11-02
IPC分类号： G06T15/00
CPC分类号： G06T13/40
摘要： Complex computer graphics forms and motions can be constructed either by hand or with motion or geometry capture technologies, once they are created, they are difficult to modify, particularly at runtime. Interpolation provides a way to leverage artist-generated source material. Methodologies for efficient runtime interpolation between multiple forms or multiple motion segments enables computers to perform more realistic animation in real-time. Shape interpolation is applied to predefined figures to create smoothly skinned figures that deform in natural ways. Predefined figures are selected using a search technique that reduces the amount of interpolation required to produce real-time animation.
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7.发明授权Method and system for providing a unified API for both 2D and 3D graphics objects 有权为2D和3D图形对象提供统一的API的方法和系统公开(公告)号：US06831635B2
公开(公告)日：2004-12-14
申请号：US09796885
申请日：2001-03-01
IPC分类号： G06F1700
CPC分类号： G06F9/541
摘要： A method for controlling the algorithmic elements in 3D graphics systems via an improved 3D graphics API is provided. In one aspect, the invention unifies separately provided 2D and 3D graphics APIs into a single graphics interface, thereby eliminating redundancy of functionality and unnecessary data types. As a result, a single mapping to various graphics objects replaces redundant mappings. A single texture download that optimizes the use of different graphics hardware is provided. A single instruction for effecting a resolution change is also provided.
摘要翻译： 提供了一种通过改进的3D图形API来控制3D图形系统中的算法元素的方法。 在一个方面，本发明将单独提供的2D和3D图形API统一为单个图形接口，从而消除功能冗余和不必要的数据类型。 因此，对各种图形对象的单一映射将替代冗余映射。 提供了优化不同图形硬件使用的单一纹理下载。 还提供了一个用于进行分辨率改变的指令。
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8.发明授权Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权将算法元素下载到协处理器的系统和方法以及相应的技术公开(公告)号：US08823718B2
公开(公告)日：2014-09-02
申请号：US10987686
申请日：2004-11-12
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。
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9.发明授权Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权将算法元素下载到协处理器的系统和方法以及相应的技术公开(公告)号：US08305381B2
公开(公告)日：2012-11-06
申请号：US12112676
申请日：2008-04-30
申请人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
发明人： Charles N. Boyd , Michele B. Boland , Michael A. Toelle , Anantha Rao Kancherla , Amar Patel , Iouri Tarassov , Stephen H. Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，其中可选地支持流模数值，在像素着色器上提供寄存器存储元件，并且与表示像素的面相关联的存储相关联的接口，提供顶点着色器和 具有更多片上寄存器存储的像素着色器，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。
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10.发明授权Method and system for defining and controlling algorithmic elements in a graphics display system 有权用于在图形显示系统中定义和控制算法元素的方法和系统公开(公告)号：US07965288B2
公开(公告)日：2011-06-21
申请号：US12604102
申请日：2009-10-22
申请人： Charles N. Boyd , Michael A. Toelle
发明人： Charles N. Boyd , Michael A. Toelle
IPC分类号： G06F17/00
CPC分类号： G06T15/005
摘要： An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.
摘要翻译： 提供了一种能够实现3D芯片的可编程性的API，其中由开发者编写的编程或算法元素可以被下载到芯片，从而对芯片进行编程以执行这些算法。 开发人员将可下载的例程写入3D图形芯片。 还提供了一组与已经为开发人员编程的API相关联的算法元素，可以下载到可编程芯片以提高性能。 因此，开发人员可以将预先存在的API对象下载到3D图形芯片。 开发人员坚持使用特定格式来打包一个由3D图形芯片实现的算法元素或指令集。 开发人员通过参考3D图形芯片了解的“令牌”列表将指令集打包成数组。 这个数组依次被正确地映射到3D图形芯片，用于由3D图形芯片实现算法元素。
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