公开(公告)号：US06232630B1

公开(公告)日：2001-05-15

申请号：US09348583

申请日：1999-07-07

申请人： Mark T. Ramsbey ,  Tuan Pham ,  Yu Sun ,  Kenneth Wo-Wai Au ,  David H. Chi

发明人： Mark T. Ramsbey ,  Tuan Pham ,  Yu Sun ,  Kenneth Wo-Wai Au ,  David H. Chi

IPC分类号： H01L2972

CPC分类号： H01L29/42324

摘要： The reliability of a tunnel oxide is improved by light doping of the floating gate, as with phosphorous or arsenic atoms. Doping can be implemented by ion implantation or by in situ deposition. The relatively low dopant concentration further enhances charge retention on the floating gate.

摘要翻译： 隧道氧化物的可靠性通过浮栅的轻掺杂而改善，如同磷或砷原子一样。 掺杂可以通过离子注入或原位沉积来实现。 相对低的掺杂剂浓度进一步增强了浮栅上的电荷保持。

公开(公告)号：US06433383B1

公开(公告)日：2002-08-13

申请号：US09357333

申请日：1999-07-20

申请人： Mark Ramsbey ,  Unsoon Kim ,  Kenneth Wo-Wai Au ,  David H. Chi ,  James Markarian

发明人： Mark Ramsbey ,  Unsoon Kim ,  Kenneth Wo-Wai Au ,  David H. Chi ,  James Markarian

IPC分类号： H01L27108

CPC分类号： H01L27/11521 ,  H01L21/3144 ,  H01L21/3145 ,  H01L27/115 ,  H01L29/511

摘要： A single interpoly dielectric layer is provided for use in semiconductor devices. The single interpoly dielectric layer being formed of silicon graded such that certain regions within the single interpoly dielectric layer are either oxygen-rich or nitrogen-rich. The single interpoly dielectric layer can be formed in-situ within a single deposition tool. In certain embodiments, the resulting single interpoly dielectric layer can be made thinner and/or can be formed to provide improved dielectric characteristics when compared to a conventional oxide-nitride-oxide (ONO) interpoly dielectric layer that has three separate and unique layers. Thus, the single interpoly dielectric layer is highly desirable for use in reduced-size semiconductor devices and/or semiconductor devices requiring improved data retention capabilities, such as non-volatile memory cells.

摘要翻译： 提供了一个用于半导体器件的单互补电介质层。 由硅分级形成的单个间隔电介质层使得单个互间介电层内的某些区域是富氧或富含氮的。 单个间隔电介质层可以在单个沉积工具内原位形成。 在某些实施例中，当与具有三个独立且独特的层的常规氧化物 - 氮化物 - 氧化物（ONO）间隔电介质层相比时，所得到的单个间隔电介质层可以制成更薄和/或可形成以提供改善的介电特性。 因此，对于需要改进的数据保持能力的尺寸较小的半导体器件和/或半导体器件（例如非易失性存储器单元），单个互聚电介质层是非常需要的。

公开(公告)号：US06204159B1

公开(公告)日：2001-03-20

申请号：US09349603

申请日：1999-07-09

申请人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  Yuesong He

发明人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  Yuesong He

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11546

摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a core region and a periphery region, the core region including a flash memory cell area and a select gate area and the periphery region including a high voltage transistor area and low voltage transistor area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer over at least a portion of the first doped amorphous silicon layer; removing portions of the first oxide layer, the first doped amorphous silicon layer, and the dielectric layer in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; growing a second oxide layer over at least a portion of the substrate in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; removing portions of the second oxide layer in the select gate area of the core region and the low voltage transistor area the periphery region; growing a third oxide layer over at least a portion of the substrate in the select gate area of the core region and the low voltage transistor area of the periphery region; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer, the second oxide layer and the third oxide layer; and forming a flash memory cell in the flash memory cell area of the core region, a select gate transistor in the select gate area of the core region, a low voltage transistor in the low voltage transistor area of the periphery region, and a high voltage transistor in the high voltage transistor area of the periphery region.

摘要翻译： 在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化层，所述衬底包括芯区域和周边区域， 芯区域包括闪存单元区域和选择栅极区域，并且包括高压晶体管区域和低压晶体管区域的周边区域; 在所述第一氧化物层的至少一部分上沉积第一掺杂非晶硅层; 在所述第一掺杂非晶硅层的至少一部分上沉积介电层; 去除所述芯区域的所述选择栅极区域中的所述第一氧化物层，所述第一掺杂非晶硅层和所述介电层的部分，以及所述高压晶体管区域和所述低电压晶体管区域的外围区域; 在所述芯区域的所述选择栅极区域中的所述衬底的至少一部分和所述高压晶体管区域和所述低电压晶体管区域的外围区域上生长第二氧化物层; 去除芯区域的选择栅极区域中的第二氧化物层的部分和外围区域的低电压晶体管区域; 在芯区域的选择栅极区域和外围区域的低电压晶体管区域的至少一部分衬底上生长第三氧化物层; 在所述电介质层，所述第二氧化物层和所述第三氧化物层的至少一部分上沉积第二掺杂非晶硅层; 以及在芯区的闪速存储单元区域中形成闪速存储单元，在芯区的选择栅极区中的选择栅极晶体管，外围区的低电压晶体管区中的低电压晶体管，以及高电压 晶体管在周边区域的高压晶体管区域。

公开(公告)号：US06235586B1

公开(公告)日：2001-05-22

申请号：US09352801

申请日：1999-07-13

申请人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  Hao Fang

发明人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  Hao Fang

IPC分类号： H01L218247

CPC分类号： H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524

摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

摘要翻译： 在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化物层，所述衬底包括闪存单元区域和选择栅极 区; 去除衬底的闪存单元区域中的第一氧化物层的一部分; 在所述闪存单元区域中的所述衬底的至少一部分上以及所述选择栅极区域中的所述第一氧化物层的至少一部分上生长第二氧化物层; 在所述第二氧化物层的至少一部分上沉积第一原位掺杂的非晶硅层，所述第一原位掺杂的非晶硅层具有从约至在的厚度; 在第一原位掺杂的非晶硅层的至少一部分上沉积介电层; 在所述电介质层的至少一部分上沉积第二掺杂非晶硅层; 以及在所述衬底的所述闪存单元区域中形成快闪存储器单元，以及在所述选择栅极区域衬底中形成选择栅极晶体管，所述闪存单元包括所述第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层， 和第二掺杂非晶硅层，选择栅晶体管包括第一氧化物层，第二氧化物层，第一原位掺杂非晶硅层，介电层和第二掺杂非晶硅层。

公开(公告)号：US06218689B1

公开(公告)日：2001-04-17

申请号：US09369638

申请日：1999-08-06

申请人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  Hao Fang

发明人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  Hao Fang

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. In a preferred embodiment, the polysilicon layer which forms both the floating gate of the flash memory cell and the select gate of the select transistor of the device is doped with between approximately 5×1018 and 8×1019 ions/cm3 of phosphorus. With this dopant level, the contact resistance of the select transistor's control gate is low, thus keeping the word line resistivity of the device low. Simultaneously, contamination of the tunnel oxide of the flash memory cell by the dopant is limited, allowing for the interface between the floating gate and the tunnel oxide to be smooth, which prevents charge gain/loss problems. Thus, the reliability of the device is increased.

摘要翻译： 本发明提供了一种方法和NAND型闪速存储器件。 该方法包括在衬底的选择晶体管区域和衬底的存储单元区域中形成选择栅极氧化物层和隧道氧化物层; 在选择栅极氧化物层和隧道氧化物层上形成掺杂非晶硅层，掺杂非晶硅层具有同时避免选择晶体管字线高电阻问题和电荷增益/电荷损失问题的掺杂剂水平; 在所述掺杂非晶硅层上形成绝缘层; 在所述绝缘层上形成控制栅极层; 以及至少蚀刻所述掺杂的非晶硅层，所述绝缘层和所述控制栅极层，以形成至少一个存储单元堆叠结构和至少一个选择晶体管堆叠结构。 在优选实施例中，形成闪存单元的浮动栅极和器件的选择晶体管的选择栅极的多晶硅层掺杂有大约5×1018和8×1019离子/ cm3的磷。 利用该掺杂剂水平，选择晶体管的控制栅极的接触电阻低，从而保持器件的字线电阻率低。 同时，掺杂剂对闪存单元的隧道氧化物的污染是有限的，允许浮置栅极和隧道氧化物之间的界面平滑，这防止了电荷增益/损耗问题。 因此，装置的可靠性增加。

公开(公告)号：US06380029B1

公开(公告)日：2002-04-30

申请号：US09205899

申请日：1998-12-04

申请人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  John Jianshi Wang

发明人： Kent Kuohua Chang ,  Kenneth Wo-Wai Au ,  John Jianshi Wang

IPC分类号： H01L21330

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括所述第一多晶硅层上的第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层; 在所述绝缘层上形成第二多晶硅层; 通过使用WF 6和SiH 2 Cl 2的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US06309927B1

公开(公告)日：2001-10-30

申请号：US09263983

申请日：1999-03-05

申请人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  David Chi

发明人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  David Chi

IPC分类号： H01L218247

CPC分类号： H01L21/28273

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer over the first polysilicon layer, and a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is made by chemical vapor deposition at a temperature from about 200° C. to about 650° C. using an organic tantalum compound and an oxygen compound, and heating in an N2O atmosphere at a temperature from about 700° C. to about 875° C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层，所述绝缘层包括在所述第一多晶硅层上的氧化物层和在所述氧化物层上的五氧化二钽层，其中所述五氧化二钽层通过化学气相沉积在约200℃ 使用有机钽化合物和氧化合物在约700℃至约875℃的温度下在N 2 O气氛中加热。 在所述绝缘层上形成第二多晶硅层; 至少蚀刻第一多晶硅层，第二多晶硅层和绝缘层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。