公开(公告)号：US08020138B2

公开(公告)日：2011-09-13

申请号：US12131476

申请日：2008-06-02

申请人： Bruce Balch ,  Nazmul Habib ,  Susan K. Lichtensteiger ,  Daniel L. Stasiak ,  Richard A. Wachnik

发明人： Bruce Balch ,  Nazmul Habib ,  Susan K. Lichtensteiger ,  Daniel L. Stasiak ,  Richard A. Wachnik

IPC分类号： G06F17/50

CPC分类号： G01R31/2884

摘要： A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.

摘要翻译： 提供了一种表征具有至少一个电压岛和至少一个性能屏幕环形振荡器（PSRO）的芯片的性能的方法。 片上性能监视器（OCPM）被并入电压岛。 电压岛的性能测量仅在电源岛上产生。 性能屏幕环形振荡器（PSRO）的性能测量仅在电源电压岛下产生。 将性能屏幕环形振荡器（PSRO）的性能测量与片内性能监视器（OCPM）的性能测量进行比较，以确定由于电压岛引起的系统偏移。 使用由于电压岛引起的系统偏移来调整性能模型。

公开(公告)号：US20090295402A1

公开(公告)日：2009-12-03

申请号：US12131476

申请日：2008-06-02

申请人： Bruce Balch ,  Nazmul Habib ,  Susan K. Lichtensteiger ,  Daniel L. Stasiak ,  Richard A. Wachnik

发明人： Bruce Balch ,  Nazmul Habib ,  Susan K. Lichtensteiger ,  Daniel L. Stasiak ,  Richard A. Wachnik

IPC分类号： G01R31/02

CPC分类号： G01R31/2884

摘要： A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.

摘要翻译： 提供了一种表征具有至少一个电压岛和至少一个性能屏幕环形振荡器（PSRO）的芯片的性能的方法。 片上性能监视器（OCPM）被并入电压岛。 电压岛的性能测量仅在电源岛上产生。 性能屏幕环形振荡器（PSRO）的性能测量仅在电源电压岛下产生。 将性能屏幕环形振荡器（PSRO）的性能测量与片内性能监视器（OCPM）的性能测量进行比较，以确定由于电压岛引起的系统偏移。 使用由于电压岛引起的系统偏移来调整性能模型。

公开(公告)号：US06202191B1

公开(公告)日：2001-03-13

申请号：US09333604

申请日：1999-06-15

申请人： Ronald G. Filippi ,  Phillip C. Lin ,  Thomas M. Shaw ,  Richard A. Wachnik

发明人： Ronald G. Filippi ,  Phillip C. Lin ,  Thomas M. Shaw ,  Richard A. Wachnik

IPC分类号： G06F1750

CPC分类号： H01L21/76858 ,  G06F17/5077 ,  H01L21/76841 ,  H01L21/7685 ,  H01L23/5286 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for forming a novel power grid structure for integrated circuit semiconductor chip devices that exhibits increased electromigration resistance by including diffusion blocking interlevel contacts and employing a regular array of conducting line elements with “phase shift” between adjacent tracks of segmented power busses. The novel grid structure includes a first metal layer including a first set of conducting line segments that are substantially parallel to one another and run in a first direction; a layer of diffusion blocking dielectric insulation above the first layer; a second metal layer including a second set of conducting line segments substantially parallel to each other and running in a second direction orthogonal to the first direction; and, interlevel contact studs disposed substantially vertically through the diffusion blocking dielectric insulation layer for electrically connecting aligned line segments of the first and second sets, wherein each segment of the first and second sets of line segments is limited to a predetermined length by a diffusion blocking boundary.

摘要翻译： 用于形成用于集成电路半导体芯片器件的新型电网结构的方法，其通过包括扩散阻挡层间接触并采用在分段功率总线的相邻轨道之间具有“相移”的导线组件的规则阵列来表现出增加的电迁移阻力。 新颖的栅格结构包括第一金属层，其包括基本上彼此平行并沿第一方向延伸的第一组导线段; 在第一层之上的一层扩散阻挡介电绝缘层; 第二金属层，包括基本上彼此平行并沿与第一方向正交的第二方向延伸的第二组导线段; 以及穿过所述扩散阻挡介电绝缘层基本垂直设置的层间接触柱，用于电连接所述第一和第二组的对准的线段，其中所述第一和第二组线段的每个段通过扩散阻挡被限制到预定长度 边界。

公开(公告)号：US6069068A

公开(公告)日：2000-05-30

申请号：US947277

申请日：1997-10-08

申请人： Hazara S. Rathore ,  Hormazdyar M. Dalal ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Richard G. Smith ,  Alexander J. Swinton ,  Richard A. Wachnik

发明人： Hazara S. Rathore ,  Hormazdyar M. Dalal ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Richard G. Smith ,  Alexander J. Swinton ,  Richard A. Wachnik

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  B05D5/06

CPC分类号： H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

摘要翻译： 提供具有改善的电迁移和耐腐蚀性的亚半微米铜互连的方法。 该方法包括使用电镀铜的双镶嵌，其中种子层通过化学气相沉积沉积，或通过物理气相沉积在小于约800埃的层中。

公开(公告)号：US20140027851A1

公开(公告)日：2014-01-30

申请号：US13618240

申请日：2012-09-14

申请人： Yue Tan ,  Zhibin Ren ,  Richard A. Wachnik ,  Haining S. Yang

发明人： Yue Tan ,  Zhibin Ren ,  Richard A. Wachnik ,  Haining S. Yang

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/7833 ,  H01L29/7841

摘要： Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N−, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P−) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.

摘要翻译： 与SOI中的FET的浮体接触可以形成在FET的两个扩散中的一个中的一个的一部分中，其中“牺牲”的扩散部分（例如N，用于NFET）用于制造 接触是不直接相邻（或在门下方）的扩散部分。 这与连接的主体FET工作良好，其中扩散不会一直延伸到BOX，因此连接体（例如P-）在形成接触的扩散下延伸。 示出了向6T SRAM单元的两个NFET（PG和PD）接地的示例。

公开(公告)号：US07224063B2

公开(公告)日：2007-05-29

申请号：US09871883

申请日：2001-06-01

申请人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

发明人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC分类号： H01L23/52

CPC分类号： H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

摘要翻译： 一种互连结构，包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下层导线的侧面和底部上的下导电衬垫; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

公开(公告)号：US06258710B1

公开(公告)日：2001-07-10

申请号：US09459167

申请日：1999-12-10

申请人： Hazara S. Rathore ,  Hormazdyar M. Dalal ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Richard G. Smith ,  Alexander J. Swinton ,  Richard A. Wachnik

发明人： Hazara S. Rathore ,  Hormazdyar M. Dalal ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Richard G. Smith ,  Alexander J. Swinton ,  Richard A. Wachnik

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

摘要翻译： 提供具有改善的电迁移和耐腐蚀性的亚半微米铜互连的方法。 该方法包括使用电镀铜的双镶嵌，其中种子层通过化学气相沉积沉积，或通过物理气相沉积在小于约800埃的层中。

公开(公告)号：US20100207213A1

公开(公告)日：2010-08-19

申请号：US12707191

申请日：2010-02-17

申请人： Yue Tan ,  Zhibin Ren ,  Richard A. Wachnik ,  Haining S. Yang

发明人： Yue Tan ,  Zhibin Ren ,  Richard A. Wachnik ,  Haining S. Yang

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/7833 ,  H01L29/7841

摘要： Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N−, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P−) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.

摘要翻译： 与SOI中的FET的浮体接触可以形成在FET的两个扩散中的一个中的一个的一部分中，其中“牺牲”的扩散部分（例如N，用于NFET）用于制造 接触是不直接相邻（或在门下方）的扩散部分。 这与连接的主体FET工作良好，其中扩散不会一直延伸到BOX，因此连接体（例如P-）在形成接触的扩散下延伸。 示出了向6T SRAM单元的两个NFET（PG和PD）接地的示例。

公开(公告)号：US06531759B2

公开(公告)日：2003-03-11

申请号：US09777540

申请日：2001-02-06

申请人： Richard A. Wachnik ,  Henry A. Nye, III ,  Charles R. Davis ,  Theodore H. Zabel ,  Phillip J. Restle

发明人： Richard A. Wachnik ,  Henry A. Nye, III ,  Charles R. Davis ,  Theodore H. Zabel ,  Phillip J. Restle

IPC分类号： H01L23552

CPC分类号： H01L23/556 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025

摘要： An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

公开(公告)号：US07470613B2

公开(公告)日：2008-12-30

申请号：US11619748

申请日：2007-01-04

申请人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

发明人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC分类号： H01L21/4763

CPC分类号： H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

摘要翻译： 一种用于形成互连结构的方法，所述互连结构包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下导电衬垫在侧面和底部 的下层电线; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。