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    Equivalent gate count yield estimation for integrated circuit devices
    3.
    发明授权
    Equivalent gate count yield estimation for integrated circuit devices 失效
    集成电路器件的等效门数产量估算

    公开(公告)号：US07477961B2

    公开(公告)日：2009-01-13

    申请号：US11382963

    申请日：2006-05-12

    申请人： Thomas S. Barnett ,  Jeanne P. Bickford ,  William Y. Chang ,  Rashmi D. Chatty ,  Sebnem Jaji ,  Kerry A. Kravec ,  Wing L. Lai ,  Gie Lee ,  Brian M. Trapp ,  Alan J. Weger

    发明人： Thomas S. Barnett ,  Jeanne P. Bickford ,  William Y. Chang ,  Rashmi D. Chatty ,  Sebnem Jaji ,  Kerry A. Kravec ,  Wing L. Lai ,  Gie Lee ,  Brian M. Trapp ,  Alan J. Weger

    IPC分类号： G06F19/00

    CPC分类号： G06F17/5081 ,  G06F2217/10

    摘要： A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

    摘要翻译： 一种用于半导体产品的产量建模的方法包括通过对每个库元件运行关键区域分析来确定多个库元件中的每一个元素的预期故障，以及从关键区域分析来估计每单位面积的预期故障数量 并将其与先前制造的半导体产品的实际观察到的故障进行比较。 此后，响应于观察到的产量，更新每个库元素的预期数量的故障。 建立了一个数据库，其中包括每个库元素的管芯大小和预期的故障。 集成电路产品芯片尺寸被估计，并且选择用于创建集成电路管芯的库元件。 获得每个所选库元素的故障和大小数据，对每个库元素的调整后的估计故障相加，并计算估计的收益率。

    System and method for estimating reliability of components for testing and quality optimization
    4.
    发明申请
    System and method for estimating reliability of components for testing and quality optimization 审中-公开
    用于估计组件可靠性的系统和方法，用于测试和质量优化

    公开(公告)号：US20080281541A1

    公开(公告)日：2008-11-13

    申请号：US12080159

    申请日：2008-03-31

    申请人： Adit D. Singh ,  Thomas S. Barnett

    发明人： Adit D. Singh ,  Thomas S. Barnett

    IPC分类号： G06F19/00

    CPC分类号： H01L22/20 ,  G01R31/287

    摘要： A system and method for determining the early life reliability of an electronic component, including classifying the electronic component based on an initial determination of a number of fatal defects, and estimating a probability of latent defects present in the electronic component based on that classification with the aim of optimizing test costs and product quality.

    摘要翻译： 一种用于确定电子部件的早期生命可靠性的系统和方法，包括基于对多个致命缺陷的初始确定来分类电子部件，并且基于该分类，估计电子部件中存在的潜在缺陷的概率， 旨在优化测试成本和产品质量。

    EQUIVALENT GATE COUNT YIELD ESTIMATION FOR INTEGRATED CIRCUIT DEVICES
    6.
    发明申请
    EQUIVALENT GATE COUNT YIELD ESTIMATION FOR INTEGRATED CIRCUIT DEVICES 审中-公开
    集成电路设备的等效门计数估计

    公开(公告)号：US20090112352A1

    公开(公告)日：2009-04-30

    申请号：US12348549

    申请日：2009-01-05

    申请人： Thomas S. Barnett ,  Jeanne P. Bickford ,  William Y. Chang ,  Rashmi D. Chatty ,  Sebnem Jaji ,  Kerry A. Kravec ,  Wing L. Lai ,  Gie Lee ,  Brian M. Trapp ,  Alan J. Weger

    发明人： Thomas S. Barnett ,  Jeanne P. Bickford ,  William Y. Chang ,  Rashmi D. Chatty ,  Sebnem Jaji ,  Kerry A. Kravec ,  Wing L. Lai ,  Gie Lee ,  Brian M. Trapp ,  Alan J. Weger

    IPC分类号： G06F19/00

    CPC分类号： G06F17/5081 ,  G06F2217/10

    摘要： A storage medium including a method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

    摘要翻译： 包括对半导体产品的产量建模的方法的存储介质包括通过对每个库元素运行关键区域分析来确定多个库元素中的每一个元素的预期故障，并且从临界区域分析来估计预期数量 每单位面积的故障，并将其与先前制造的半导体产品的实际观察到的故障进行比较。 此后，响应于观察到的产量，更新每个库元素的预期数量的故障。 建立了一个数据库，其中包括每个库元素的管芯大小和预期的故障。 集成电路产品芯片尺寸被估计，并且选择用于创建集成电路管芯的库元件。 获得每个所选库元素的故障和大小数据，对每个库元素的调整后的估计故障相加，并计算估计的收益率。

    Carpenter saw transporter assembly
    7.
    发明授权
    Carpenter saw transporter assembly 失效
    木匠锯运输机组装

    公开(公告)号：US07416193B1

    公开(公告)日：2008-08-26

    申请号：US11846037

    申请日：2007-08-28

    申请人： Thomas S. Barnett

    发明人： Thomas S. Barnett

    IPC分类号： B25H1/00

    CPC分类号： B25H3/006 ,  B23D47/025

    摘要： The carpenter saw transporter assembly (20) includes a rectangular plate (32) with a flange (44) for supporting the saw machine (22). A plurality of wheel assemblies (46) are mounted on the flange (44) for transporting the saw machine (22). A mounting rail (52) has a width (Wt) less than the width (Wp) of the plate (32) and is disposed on the plate (32) and presents male or female undercuts (58) between a top portion (54) and a bottom portion (56). The saw machine (22) includes clamps (28) that can be inserted under and mechanically retained by the undercuts (58). A handle tunnel (62) extends into the mounting rail (52) for disposing a slidable handle (60). A locking mechanism (76) is disposed on the mounting rail (52) for locking the handle (60) in various positions. A plurality of docking strips (82) are disposed on the plate (32) for elevating the position of which the clamps (28) are received and eliminating mechanical contacts between the plate (32) and the cranks (30).

    摘要翻译： 木匠锯运送器组件（20）包括具有用于支撑锯床（22）的凸缘（44）的矩形板（32）。 多个轮组件（46）安装在用于运送锯床（22）的凸缘（44）上。 安装轨道（52）具有小于板（32）的宽度（W SUB P）的宽度（W SUB），并且设置在板（32）上， 并且在顶部（54）和底部（56）之间呈现阳或阴底切（58）。 锯床（22）包括夹子（28），其可插入下切口（58）的机械保持。 手柄通道（62）延伸到安装轨道（52）中，用于设置可滑动的把手（60）。 锁定机构（76）设置在安装轨道（52）上，用于将手柄（60）锁定在各种位置。 多个对接条（82）设置在板（32）上，用于升高夹具（28）被容纳的位置，并消除板（32）和曲柄（30）之间的机械接触。

    Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability
    9.
    发明授权
    Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability 有权
    用于确定集成电路设备实现最佳可靠性所需的最小后期制作测试时间的方法和系统

    公开(公告)号：US07139944B2

    公开(公告)日：2006-11-21

    申请号：US10604887

    申请日：2003-08-25

    申请人： Tange Nan Barbour ,  Thomas S. Barnett ,  Matthew Sean Grady ,  William Vincent Huott ,  Michael Richard Ouellette

    发明人： Tange Nan Barbour ,  Thomas S. Barnett ,  Matthew Sean Grady ,  William Vincent Huott ,  Michael Richard Ouellette

    IPC分类号： G11C29/00 ,  G06F11/00

    CPC分类号： G11C29/44 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/4402

    摘要： A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.

    摘要翻译： 一种用于在集成电路器件上确定最小后期制作测试时间以实现利用缺陷计数的该器件的最佳可靠性的方法和系统。 对集成电路装置上的缺陷单元或缺陷单元（DEFECTS）的有缺陷单元的数量进行计数，该计数作为确定最小测试时间的基础。 更高数量的缺陷导致更长的后期测试，以实现集成电路器件的最佳可靠性。 DEFECTS的数量可以在集成电路设备内部的设备上进行计数，并可用于确定最低要求的测试时间。 还可以通过拦截路由到另一设备的信息，在集成电路设备外部获得缺陷数量。 内部和外部提供的信息还可以显示缺陷的物理位置，以进一步完善最低要求的测试时间。

    Method of statistical binning for reliability selection
    10.
    发明授权
    Method of statistical binning for reliability selection 失效
    可靠性选择的统计分类方法

    公开(公告)号：US06789032B2

    公开(公告)日：2004-09-07

    申请号：US10326668

    申请日：2002-12-19

    申请人： Tange N. Barbour ,  Thomas S. Barnett ,  Matthew S. Grady ,  Kathleen G. Purdy

    发明人： Tange N. Barbour ,  Thomas S. Barnett ,  Matthew S. Grady ,  Kathleen G. Purdy

    IPC分类号： G06F1900

    CPC分类号： G06F17/18

    摘要： A statistical method is described for reliability selection of dies on semiconductor wafers using critical wafer yield parameters. This is combined with other data from the wafer or module level reliability screens (such as voltage screen or burn-in) to obtain the relative latent defect density. Finally the modeled results are compared with actual results to demonstrate confidence in the model.

    摘要翻译： 描述了使用关键晶圆产量参数对半导体晶片上的管芯的可靠性选择的统计方法。 这与来自晶片或模块级可靠性屏幕（例如电压屏或老化）的其他数据相结合，以获得相对潜在缺陷密度。 最后将建模结果与实际结果进行比较，以证明该模型的信心。