公开(公告)号：US07336717B2

公开(公告)日：2008-02-26

申请号：US10384996

申请日：2003-03-10

申请人： Markus Hammes ,  Stefan Heinen ,  Stefan Van Waasen ,  Andre Hanke ,  Sönke Mehrgardt ,  Elmar Wagner

发明人： Markus Hammes ,  Stefan Heinen ,  Stefan Van Waasen ,  Andre Hanke ,  Sönke Mehrgardt ,  Elmar Wagner

IPC分类号： H04L5/12 ,  H04L23/02

CPC分类号： H03D1/2245

摘要： A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex intermediate frequency signal can be derived. Connected downstream of the first mixer stage is a limiting amplifier at whose output the intermediate frequency signal is present in a discrete-value and continuous-time fashion. A sampling device, for sampling the intermediate frequency signal, and a digital demodulator unit are connected to the output of this limiter. The demodulated input signal can be derived at the output of this digital demodulator unit. The present radio receiver requires a low chip area in conjunction with low power consumption, but offers a high sensitivity and accuracy based on the digitally implemented demodulation.

摘要翻译： 具有低中频的无线电接收机具有可以馈送调制输入信号的第一混频器级，并且在其输出端可以导出复合中频信号。 连接在第一混频器级的下游是限幅放大器，其输出中间频率信号以离散值和连续时间方式存在。 用于采样中频信号的采样装置和数字解调器单元连接到该限幅器的输出。 解调输入信号可以在该数字解调器单元的输出端导出。 本无线电接收机需要低功耗的低芯片面积，但是基于数字实现的解调提供了高灵敏度和精度。

公开(公告)号：US07127221B2

公开(公告)日：2006-10-24

申请号：US10384999

申请日：2003-03-10

申请人： Markus Hammes ,  Stefan Heinen ,  Stefan Van Waasen ,  Andre Hanke ,  Elmar Wagner

发明人： Markus Hammes ,  Stefan Heinen ,  Stefan Van Waasen ,  Andre Hanke ,  Elmar Wagner

IPC分类号： H04B17/02 ,  H03M3/00

CPC分类号： H03D1/2245

摘要： In a receiver circuit for demodulating a high-frequency signal, a limiting amplifier stage with a downstream sigma-delta converter is connected in series with a mixer stage that transforms a high-frequency signal that is supplied at its input into an intermediate-frequency signal. The intermediate-frequency signal at the output of the limiting amplifier stage is value-discrete and time-continuous. The described receiver architecture has a high sensitivity, is substantially independent of production tolerances, and occupies a small area; therefore, it is particularly suitable for mobile radio applications.

公开(公告)号：US06985029B2

公开(公告)日：2006-01-10

申请号：US10298832

申请日：2002-11-18

申请人： Elmar Wagner ,  Stefan Heinen ,  Andre Hanke

发明人： Elmar Wagner ,  Stefan Heinen ,  Andre Hanke

IPC分类号： H03D3/00

CPC分类号： H03D3/002

摘要： A demodulator has a resistor and a capacitor that may be subject to tolerances. For tolerance correction, the FM demodulator is preferably supplied with a reference frequency, which corresponds to the nominal mid-frequency of the demodulator, which is a function of the resistor and the capacitor. Any discrepancy between the actual mid-frequency of the demodulator and its nominal mid-frequency leads to the production of a voltage that differs from a nominal voltage at the output. A detector detects this error and adjusts the values of the resistor or capacitor until the error between the nominal voltage and the voltage is zero or is a minimum. The described principle can be used, for example, in integrated mobile radio receivers.

摘要翻译： 解调器具有电阻器和可能容许的电容器。 对于容限校正，FM解调器优选地被提供有参考频率，其对应于解调器的标称中频，其是电阻器和电容器的函数。 解调器的实际中频与其标称中频之间的任何差异导致产生与输出端的额定电压不同的电压。 检测器检测该误差并调整电阻器或电容器的值，直到额定电压和电压之间的误差为零或最小。 所描述的原理可以用于例如集成的移动无线电接收机。

公开(公告)号：US06778510B1

公开(公告)日：2004-08-17

申请号：US09149830

申请日：1998-09-08

申请人： Christian Kranz ,  Stefan Heinen

发明人： Christian Kranz ,  Stefan Heinen

IPC分类号： H04Q700

CPC分类号： H04B7/2656

摘要： A digital telecommunication facility has a base station and one or more cordless mobile units. The telecommunication facility exchanges data between the mobile units and the base station in units of two or more TDMA frames.

摘要翻译： 数字电信设施具有基站和一个或多个无绳移动单元。 电信设备以两个或更多个TDMA帧为单位在移动单元和基站之间交换数据。

公开(公告)号：US06369623B1

公开(公告)日：2002-04-09

申请号：US09607322

申请日：2000-06-30

申请人： Stefan Heinen

发明人： Stefan Heinen

IPC分类号： H03K2100

CPC分类号： H03K23/667 ,  H03L7/193

摘要： A circuit configuration of a frequency divider includes a prescaler with at least two different division ratios and at least two further different division ratios. A main counter connected to an output of the prescaler has an adjustable division ratio. A first lower-level swallow counter has an adjustable division ratio and can change the division ratio of the prescaler. At least one second lower-level swallow counter has an adjustable division ratio, is provided at the output of the main counter and can change the division ratio of the prescaler between the two further division ratios.

摘要翻译： 分频器的电路配置包括具有至少两个不同分频比和至少两个另外不同分频比的预分频器。 连接到预分频器的输出的主计数器具有可调分频比。 第一个下级吞咽计数器具有可调分频比，可以改变预分频器的分频比。 在主计数器的输出处提供至少一个第二下级吞咽计数器具有可调分频比，并且可以改变预分频器在两个另外的分频比之间的分频比。

公开(公告)号：US06567949B2

公开(公告)日：2003-05-20

申请号：US09725347

申请日：2000-11-29

申请人： Stefan Heinen ,  Wen Xu

发明人： Stefan Heinen ,  Wen Xu

IPC分类号： H03M1300

CPC分类号： H04L1/0057 ,  G10L19/002 ,  G10L19/005 ,  G10L19/10 ,  G10L19/18 ,  G10L2019/0008

摘要： For the purpose of error masking, binary representation of parameter values are precoded at the transmitting end by a linear block code before transmission over a faulty channel, and the redundant information added in this way is not used at the receiving end for error detection within the binary parameter representations, but is utilized in the course of a parameter estimation to improve the quality of the estimated parameter values.

摘要翻译： 为了进行错误掩蔽，参数值的二进制表示在发送端通过故障信道传输之前的线性块码进行预编码，并且以这种方式添加的冗余信息在接收端不被用于内部的错误检测 二进制参数表示，但是在参数估计过程中被利用以提高估计参数值的质量。

公开(公告)号：US5604460A

公开(公告)日：1997-02-18

申请号：US500041

申请日：1995-07-10

申请人： Peter Sehrig ,  Josef Fenk ,  Stefan Heinen

发明人： Peter Sehrig ,  Josef Fenk ,  Stefan Heinen

IPC分类号： H03G1/00 ,  H03G3/00 ,  H03F1/14

CPC分类号： H03G1/0088 ,  H03G3/001

摘要： An amplifier array having digitally adjustable total gain and being constructed of a multiplicity of switchable individual amplifiers, includes at least two parallel, selectively triggerable gain paths having input and output sides. Each of the gain paths has an input amplifier and a switching amplifier being connected downstream of the input amplifier and being switchable in stages. A multiplexer has inputs connected to the output side of the gain paths and has an output. An amplifier array input is connected to the input side of the gain paths and an amplifier array output is formed by the output of the multiplexer. In a mobile radio receiver having the amplifier array, a total gain of the amplifier array is adjusted for setting an output signal of the mobile radio receiver at a constant level.

摘要翻译： 具有数字可调整总增益并由多个可切换单独放大器构成的放大器阵列包括具有输入和输出侧的至少两个平行的，可选择的可触发的增益路径。 每个增益路径具有输入放大器和开关放大器，其连接在输入放大器的下游并且可分阶段地切换。 多路复用器具有连接到增益路径的输出侧的输入并具有输出。 放大器阵列输入连接到增益路径的输入侧，放大器阵列输出由多路复用器的输出形成。 在具有放大器阵列的移动无线电接收机中，调整放大器阵列的总增益以将移动无线电接收机的输出信号设定在恒定水平。

公开(公告)号：US5557649A

公开(公告)日：1996-09-17

申请号：US442790

申请日：1995-05-17

申请人： Bruno Scheckel ,  Stefan Heinen ,  Jean Wilwert ,  Helmut Herrmann

发明人： Bruno Scheckel ,  Stefan Heinen ,  Jean Wilwert ,  Helmut Herrmann

IPC分类号： H03K23/66

CPC分类号： H03K23/667

摘要： A circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, includes first, second and third series-connected flip-flops each having an output, a data input and a clock input. The output of the second flip-flop is coupled to the data input of the third flip-flop, and the clock inputs of the first, second and third flip-flops are acted upon by a clock signal. A first AND gate is connected upstream of the first flip-flop and has a first input being acted upon by a control signal for switching over the divider ratio, and a second input being acted upon by an inverted signal from the output of the third flip-flop. A second AND gate is connected between the first and second flip-flops and has an output connected to the data input of the second flip-flop, a first input receiving an inverted signal from the output of the first flip-flop, and a second input being acted upon by the inverted signal from the output of the third flip-flop.

摘要翻译： 通过差分技术制造的电路结构，用于通过发射极耦合逻辑对具有4/5的可切换分频比分频的时钟信号包括第一，第二和第三串联连接的触发器，每个具有输出，数据输入和时钟输入 。 第二触发器的输出耦合到第三触发器的数据输入，并且第一，第二和第三触发器的时钟输入由时钟信号作用。 第一与门连接在第一触发器的上游，并且具有由控制信号作用的第一输入，用于切换分频比，并且第二输入由来自第三触发器的输出的反相信号 -flop。 第二AND门连接在第一触发器和第二触发器之间，并且具有连接到第二触发器的数据输入的输出端，第一输入端从第一触发器的输出端接收反相信号， 输入由来自第三触发器的输出的反相信号起作用。

公开(公告)号：US06738602B1

公开(公告)日：2004-05-18

申请号：US09419010

申请日：1999-10-13

申请人： Stefan Heinen ,  Stefan Beyer

发明人： Stefan Heinen ,  Stefan Beyer

IPC分类号： H04B140

CPC分类号： H04B1/408

摘要： A circuit is provided for time division duplexing with a frequency hopping technique and has a total of just two frequency synthesizers for the transmission and reception paths and only one up-converter in the transmission path. The UHF synthesizer frequency is additionally subjected to frequency division prior to insertion as a heterodyne frequency of the assigned converter in the transmission and reception paths, which, owing to the shorter transient recovery times, makes it possible to utilize the UHF frequency synthesizers at different frequencies for the transmission and reception slots, respectively. A particular application is in cordless telephones.

摘要翻译： 提供了一种用于与跳频技术进行时分双工的电路，并且在传输路径中仅具有两个用于发送和接收路径的频率合成器和仅一个上变频器。 UHF合成器频率在插入之前被额外地进行分频，作为发送和接收路径中所分配的转换器的外差频率，由于较短的瞬时恢复时间，可以使用不同频率的UHF频率合成器 分别用于发送和接收时隙。 一个特定的应用是无绳电话。

公开(公告)号：US5994931A

公开(公告)日：1999-11-30

申请号：US10172

申请日：1998-01-21

申请人： Stefan Heinen ,  Udo Matter ,  Abdul-Karim Hadjizada

发明人： Stefan Heinen ,  Udo Matter ,  Abdul-Karim Hadjizada

IPC分类号： H04L12/12 ,  H04L12/40 ,  H03K3/00

CPC分类号： H04L12/12 ,  Y02B60/34

摘要： The ON and OFF states of a second device are controlled by a first device through a three-conductor bus. The bus carries data, clock, and enable signals and the second device is in the OFF state when all the signals of the three-conductor bus have an L level. The second device is in the ON state when at least one of the signals has an H level (higher potential than the L level). The enable signal is set to the H level during the data transmission. Otherwise, it carries an L level, while the data or clock signal has an H level. The system obviates an additional housing pin. The operating state information is transmitted relatively rapidly.

摘要翻译： 第二装置的ON和OFF状态由第一装置通过三导体总线控制。 当三线总线的所有信号均为L电平时，总线承载数据，时钟和使能信号，第二个器件处于OFF状态。 当至少一个信号具有H电平（比L电平更高的电位）时，第二装置处于ON状态。 在数据传输期间，使能信号被设置为H电平。 否则，它携带L电平，而数据或时钟信号具有H电平。 该系统避免了额外的外壳销。 操作状态信息相对快速地发送。