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1.发明授权公开(公告)号：US07233467B2
公开(公告)日：2007-06-19
申请号：US11087384
申请日：2005-03-23
申请人： Markus Paul Josef Mergens , Frederic Marie Dominique De Ranter , Benjamin Van Camp , Koen Gerard Maria Verhaege , Phillip Czeslaw Jozwiak , John Armer , Bart Keppens
发明人： Markus Paul Josef Mergens , Frederic Marie Dominique De Ranter , Benjamin Van Camp , Koen Gerard Maria Verhaege , Phillip Czeslaw Jozwiak , John Armer , Bart Keppens
CPC分类号： H01L27/0251 , H03K17/08122
摘要： A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.
摘要翻译： 一种用于使用源或体积泵为电路提供ESD事件保护以在ESD事件期间增加体积和/或源极电位电平的方法和装置。 该装置包括保护电路，其响应于ESD事件，通过调节第二端子上的电位电平来限制在晶体管的两个端子之间形成的电压。
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2.发明授权Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling 有权最小尺寸，全硅化MOS驱动器和ESD保护设计，实现优化的手指间耦合公开(公告)号：US07005708B2
公开(公告)日：2006-02-28
申请号：US10435817
申请日：2003-05-12
申请人： Markus Paul Josef Mergens , Koen Gerard Maria Verhaege , Cornelius Christian Russ , John Armer , Phillip Czeslaw Jozwiak , Bart Keppens
发明人： Markus Paul Josef Mergens , Koen Gerard Maria Verhaege , Cornelius Christian Russ , John Armer , Phillip Czeslaw Jozwiak , Bart Keppens
IPC分类号： H01L23/62
CPC分类号： H01L27/0277 , H01L29/0692 , H01L29/1083 , H01L29/1087 , H01L29/41758 , H01L29/4238 , H01L29/4975 , H01L29/78 , H01L2224/05554 , H01L2224/48091 , H01L2924/00014
摘要： An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.
摘要翻译： 一种包括多个交错指状物的静电放电（ESD）MOS晶体管，其中MOS晶体管形成在用于IC的ESD保护的I / O外围和集成电路（IC）中。 MOS晶体管包括设置在P基板上的P基板和Pwell。 多个交错指状物各自包括N +源极区域，N +漏极区域和形成在设置在源极和漏极区域之间的沟道区域上的栅极区域。 每个源极和漏极包括由相邻手指共享的一排触点，其中每个触点行中的每个接触孔具有与IC的核心功能元件的最小设计规则下限定的栅极区域的距离。 Pwell形成一个公共寄生双极结晶体管基极，用于在ESD事件期间同时触发MOS晶体管的每个指状。
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3.发明授权Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies 有权低电压可控硅整流器（SCR），用于绝缘体上硅技术的静电放电（ESD）保护公开(公告)号：US06909149B2
公开(公告)日：2005-06-21
申请号：US10825780
申请日：2004-04-15
申请人： Cornelius Christian Russ , Phillip Czeslaw Jozwiak , Markus Paul Josef Mergens , John Armer , Cong-Son Trinh , Russell Mohn , Koen Gerard Maria Verhaege
发明人： Cornelius Christian Russ , Phillip Czeslaw Jozwiak , Markus Paul Josef Mergens , John Armer , Cong-Son Trinh , Russell Mohn , Koen Gerard Maria Verhaege
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device
摘要翻译： 绝缘体上硅（SOI）静电放电（ESD）保护器件，可以通过限制ESD事件期间的功率损耗来保护非常敏感的薄栅极氧化物，这最好通过降低主动（保护）器件上的电压降来实现 在ESD事件期间。 在一个实施例中，本发明提供非常低的触发和保持电压。 此外，本发明的SOI保护器件具有低阻抗和低功耗特性，可减少电压的积聚，从而使设计者能够制造出更为面积更高的保护器件
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4.发明授权公开(公告)号：US07064393B2
公开(公告)日：2006-06-20
申请号：US10783844
申请日：2004-02-20
申请人： Markus Paul Josef Mergens , Cornelius Christian Russ , John Armer , Koen Gerard Maria Verhaege , Phillip Czeslaw Jozwiak
发明人： Markus Paul Josef Mergens , Cornelius Christian Russ , John Armer , Koen Gerard Maria Verhaege , Phillip Czeslaw Jozwiak
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L27/0292
摘要： An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.
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5.发明授权公开(公告)号：US06803633B2
公开(公告)日：2004-10-12
申请号：US10099263
申请日：2002-03-15
申请人： Markus Paul Josef Mergens , Cornelius Christian Russ , John Armer , Koen Gerard Maria Verhaege , Phillip Czeslaw Jozwiak
发明人： Markus Paul Josef Mergens , Cornelius Christian Russ , John Armer , Koen Gerard Maria Verhaege , Phillip Czeslaw Jozwiak
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L27/0292
摘要： An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.
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公开(公告)号：US06583972B2
公开(公告)日：2003-06-24
申请号：US09881422
申请日：2001-06-14
申请人： Koen Gerard Maria Verhaege , Markus Paul Josef Mergens , Cornelius Christian Russ , John Armer , Phillip Czeslaw Jozwiak
发明人： Koen Gerard Maria Verhaege , Markus Paul Josef Mergens , Cornelius Christian Russ , John Armer , Phillip Czeslaw Jozwiak
IPC分类号： H02H900
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate terminals of at least one of the at least two FETs are configured to be biased by an ESD potential applied to the drain electrodes to reduce the turn-on potential of the ESD device. At least two second resistive channels are connected between a corresponding one of the source terminals of the at least two FETs and a circuit return path.
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7.发明授权Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies 有权具有混合和超低电压电源的高速技术的静电放电保护结构公开(公告)号：US07589944B2
公开(公告)日：2009-09-15
申请号：US10899383
申请日：2004-07-26
CPC分类号： H01L27/0262 , H03K17/0812 , H03K17/0814 , H03K17/305
摘要： An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. In one embodiment, the ESD protection circuit includes a pad adapted for connection to a first voltage source of a protected circuit node of the IC, and a silicon controlled rectifier (SCR) having an anode adapted for coupling to the first voltage source, and a cathode adapted for coupling to a second voltage source. At least one capacitive turn-on device respectively coupled between at least one of a first gate of the SCR and the first voltage source, and a second gate of the SCR and the second voltage source.
摘要翻译： 具有保护电路的半导体集成电路（IC）中的静电放电（ESD）保护电路。 在一个实施例中，ESD保护电路包括适于连接到IC的受保护电路节点的第一电压源的焊盘和具有适于耦合到第一电压源的阳极的可控硅整流器（SCR），以及 适于耦合到第二电压源的阴极。 分别耦合在SCR的第一栅极和第一电压源中的至少一个与SCR的第二栅极和第二电压源之间的至少一个电容性接通装置。
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8.发明授权Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies 有权具有混合和超低电压电源的高速技术的静电放电保护结构公开(公告)号：US07548401B2
公开(公告)日：2009-06-16
申请号：US11473360
申请日：2006-06-22
CPC分类号： H01L27/0262 , H01L29/7436
摘要： An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry is provided herein. In one embodiment, a circuit for protecting an integrated circuit from ESD includes a protected circuit node in the integrated circuit, a multiple stage transistor pump circuit coupled to the protected circuit node, and an electrostatic discharge protection circuit having a trigger coupled to the multiple stage transistor pump circuit. The multiple stage transistor pump circuit may comprise a Darlington transistor pump circuit.
摘要翻译： 本发明提供了具有保护电路的半导体集成电路（IC）中的静电放电（ESD）保护电路。 在一个实施例中，用于保护集成电路免受ESD的电路包括集成电路中的保护电路节点，耦合到受保护电路节点的多级晶体管泵电路和具有耦合到多级的触发器的静电放电保护电路 晶体管泵电路。 多级晶体管泵电路可以包括达林顿晶体管泵电路。
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9.发明授权公开(公告)号：US07274047B2
公开(公告)日：2007-09-25
申请号：US11032462
申请日：2005-01-10
IPC分类号： H01L29/749
CPC分类号： H01L27/0262 , H01L29/87
摘要： An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first reference potential of the protected circuitry, and at least one second type high dopant region coupled to a second reference potential of the IC. The SCR is triggered by an external on-chip trigger device, which is adapted for injecting a trigger current into at least one gate of the SCR.
摘要翻译： 具有保护电路的半导体集成电路（IC）中的静电放电（ESD）保护电路。 ESD保护电路包括可控硅整流器（SCR），其具有耦合到受保护电路的第一参考电位的至少一个第一类型高掺杂区域，以及耦合到IC的第二参考电位的至少一个第二类型高掺杂区域 。 SCR由外部片上触发装置触发，外部片上触发装置适于将触发电流注入到SCR的至少一个栅极中。
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10.发明授权公开(公告)号：US06850397B2
公开(公告)日：2005-02-01
申请号：US10648545
申请日：2003-08-25
CPC分类号： H01L27/0262 , H01L29/87
摘要： An electrostatic discharge (ESD) protection device, for protecting power lines of an integrated circuit. In one embodiment, the ESD protection device includes a first silicon controlled rectifier (SCR) coupled between a first power line and a second power line, and a second SCR coupled anti-parallel to the first SCR between the first and second power lines. A first trigger device is coupled to the first power line and a first trigger gate of the first SCR, and a second trigger device coupled to the second power line and a first trigger gate of the second SCR. The trigger devices and the SCRs provide power-down-mode-compatible operation of the power lines, as well as ESD protection.
摘要翻译： 一种静电放电（ESD）保护装置，用于保护集成电路的电源线。 在一个实施例中，ESD保护装置包括耦合在第一电力线和第二电力线之间的第一可控硅整流器（SCR）和与第一和第二电力线之间的第一SCR反并联的第二SCR。 第一触发装置耦合到第一SCR的第一电源线和第一触发栅极，以及耦合到第二电力线的第二触发装置和第二SCR的第一触发栅极。 触发器件和SCR提供电源线的掉电模式兼容操作以及ESD保护。
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