公开(公告)号：US20100109744A1

公开(公告)日：2010-05-06

申请号：US12613959

申请日：2009-11-06

申请人： Martin Czech ,  Juergen Giehl ,  Ulrich Theus

发明人： Martin Czech ,  Juergen Giehl ,  Ulrich Theus

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H03K19/018521

摘要： A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS1) and a first operating potential (VDD1) into an output signal (out) in a second operating voltage range (II) having a second ground potential (VSS2) and a second operating potential (VDD2). An input circuit (1) receives the input signal and an output circuit (2) provides the output signal (out), where the input circuit includes a parallel circuit made up by a first cascode circuit and a second cascode circuit, and the first and second cascode circuits each being formed by a first transistor in the source circuit and a second transistor in the gate circuit, a dynamic control being provided for the second transistors.

摘要翻译： 一种电平移位器，用于将具有第一接地电位（VSS1）和第一操作电位（VDD1）的第一工作电压范围（I）的输入信号（in）转换成第二工作电压范围内的输出信号（out） II）具有第二接地电位（VSS2）和第二工作电位（VDD2）。 输入电路（1）接收输入信号，并且输出电路（2）提供输出信号（out），其中输入电路包括由第一共源共栅电路和第二共源共栅电路组成的并联电路，第一和 每个由源极电路中的第一晶体管和栅极电路中的第二晶体管形成的第二共源共栅电路，为第二晶体管提供动态控制。

公开(公告)号：US20100109743A1

公开(公告)日：2010-05-06

申请号：US12613901

申请日：2009-11-06

申请人： Martin Czech ,  Juergen Giehl ,  Ulrich Theus

发明人： Martin Czech ,  Juergen Giehl ,  Ulrich Theus

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H03K17/102

摘要： A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS1) and a first operating potential (VDD1) in a second operating voltage range (II) having a second ground potential (VSS2) and a second operating potential (VDD2), having an input circuit to which the input signal (in) may be applied and an output circuit at which the output signal (out) may be picked off, the input circuit having at least one native transistor.

摘要翻译： 一种电平移位器，用于在具有第二接地电位的第二工作电压范围（II）中将具有第一接地电位（VSS1）和第一操作电位（VDD1）的第一工作电压范围（I）的输入信号（in） （VSS2）和第二工作电位（VDD2），其具有可以被施加输入信号（in）的输入电路和输出电路，输出信号（out）可以在该输出电路被拾取，输入电路至少具有 一个原生晶体管。

公开(公告)号：US08344784B2

公开(公告)日：2013-01-01

申请号：US12960806

申请日：2010-12-06

申请人： Martin Czech ,  Ulrich Theus

发明人： Martin Czech ,  Ulrich Theus

IPC分类号： H03L5/00

CPC分类号： H03K19/018585

摘要： A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

摘要翻译： 提供一种用于控制集成电路的开关晶体管的方法和电路装置，具有桥接电路和控制单元，其被设计和/或具有程序，使得控制单元被设计为测量装置并测量桥 输出用于调整桥接电路的分量的调整信号，并输出用于激活开关晶体管的控制信号。 当桥式电路）具有串联连接的电阻网络和晶体管的分支，并且控制单元被设计和/或具有程序，使得用于调整电阻网络的电阻值的调整信号可以作为组件 取决于桥电压。

公开(公告)号：US20110133782A1

公开(公告)日：2011-06-09

申请号：US12960806

申请日：2010-12-06

申请人： Martin Czech ,  Ulrich Theus

发明人： Martin Czech ,  Ulrich Theus

IPC分类号： G01R19/165 ,  H03K17/687

CPC分类号： H03K19/018585

摘要： A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

摘要翻译： 提供一种用于控制集成电路的开关晶体管的方法和电路装置，具有桥接电路和控制单元，其被设计和/或具有程序，使得控制单元被设计为测量装置并测量桥 输出用于调整桥接电路的分量的调整信号，并输出用于激活开关晶体管的控制信号。 当桥式电路）具有串联连接的电阻网络和晶体管的分支，并且控制单元被设计和/或具有程序，使得用于调整电阻网络的电阻值的调整信号可以作为组件 取决于桥电压。

公开(公告)号：US20090160524A1

公开(公告)日：2009-06-25

申请号：US12257505

申请日：2008-10-24

申请人： Ulrich Theus ,  Jurgen Giehl ,  Martin Czech

发明人： Ulrich Theus ,  Jurgen Giehl ,  Martin Czech

IPC分类号： H03L5/00

CPC分类号： H03K3/35613

摘要： The invention relates to a level slider circuit having a first level slider (1) and a second level slider (2) switched in series for the conversion of an input signal (Vin) from a first operating voltage range (A) at a first ground voltage (VSSA) and a first supply voltage (VDDA) into an output signal (Vout) in a second operating voltage range (B) at a second ground voltage (VSSB) and a second supply voltage (VDDB), wherein the first level slider (1) is embodied for the conversion of the input signal (Vin) to the ground voltage (VSSA) of the second operating voltage range (B) for the conversion of the input signal (Vin), and that the second level slider (2) is embodied for the conversion of an intermediate signal (VZ) output by the first level slider (1) to the output signal travel (ΔVout).

摘要翻译： 本发明涉及一种具有第一电平滑块（1）和第二电平滑块（2）的电平滑块电路，该第一电平滑块（1）和第二电平滑块（2）串联切换以便在第一地面处从第一工作电压范围（A）转换输入信号（Vin） 在第二接地电压（VSSB）和第二电源电压（VDDB）中的第二工作电压范围（B）中的输出信号（Vout）中的第一电平（VSSA）和第一电源电压（VDDA） （1）被实现为用于转换输入信号（Vin）的输入信号（Vin）到第二工作电压范围（B）的接地电压（VSSA）的转换，并且第二电平滑块（2） ）用于将由第一级滑块（1）输出的中间信号（VZ）转换为输出信号行程（DeltaVout）。

公开(公告)号：US06891206B2

公开(公告)日：2005-05-10

申请号：US09780976

申请日：2001-02-09

申请人： Martin Czech ,  Jürgen Kessel ,  Eckart Wagner ,  Ulrich Theus

发明人： Martin Czech ,  Jürgen Kessel ,  Eckart Wagner ,  Ulrich Theus

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L23/62 ,  H01L31/111

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

摘要翻译： 为了防止在CMOS技术中的单片集成电路中的静电放电，提出了一种横向晶闸管结构，其与传统的晶闸管结构相比具有低得多的触发电压。

公开(公告)号：US20080211512A1

公开(公告)日：2008-09-04

申请号：US11807181

申请日：2007-05-25

申请人： Martin Czech

发明人： Martin Czech

IPC分类号： G01R31/02

CPC分类号： G01R31/2853

摘要： The invention relates to a testing method and to a test circuit arrangement for testing a circuit section of a circuit, having a connection section connected to the circuit section used to conduct a current from or to the circuit section, and having a detector circuit; wherein a first tapping point is arranged on the connection section at a distance from a transition to the circuit section, a second tapping point is arranged at the connection section that is closer to the circuit section than the first tapping point, and wherein the detector circuit samples a voltageor a voltage-equivalent value between the first and the second tapping point for testing of the circuit section.

摘要翻译： 本发明涉及一种用于测试电路的电路部分的测试方法和测试电路装置，该电路部分具有连接到电路部分的连接部分，该电路部分用于将电流传导到电路部分，或具有检测器电路; 其特征在于，在与所述电路部的过渡相距一定距离处，在所述连接部上配置有第一分接点，所述连接部配置有比所述第一分接点更靠近所述电路部的第二分接点， 对第一和​​第二出口点之间的电压等效值进行采样，以测试电路部分。

公开(公告)号：US07538996B2

公开(公告)日：2009-05-26

申请号：US11259378

申请日：2005-10-26

申请人： Martin Czech ,  Michael Albert

发明人： Martin Czech ,  Michael Albert

IPC分类号： H02H9/00

CPC分类号： H01L27/0251

摘要： A circuit with protection against electrostatic destruction comprises at least two sections (A, B) composed of a first and second section (A, B). Each of the sections (A, B) has its own working voltage system with a fundamental voltage (USS or USS1) and a supply voltage (UDD or UDD1), and at least one connection (SC) between an information terminal (SA) of the first section (A) and an information terminal (SB) of the second section (B) to transfer information between the first section (A) and the second section (B). The connection (SC) has a transistor circuit with at least one transistor (X) of the first section (A), a resistance (R1), and a first transistor (E) of the second section (B), wherein the first transistor (X) is connected between the fundamental voltage (USS) of the first section (A) and the resistance (R1), and the first transistor (E) of the second section (B) is connected between the resistance (R1) and the supply voltage (UDD1) of the second section (B).

摘要翻译： 具有防止静电破坏的电路包括由第一和第二部分（A，B）组成的至少两个部分（A，B）。 每个部分（A，B）具有其自身的工作电压系统，其基本电压（USS或USS1）和电源电压（UDD或UDD1）以及至少一个连接（SC）在信息终端（SA） 用于在第一部分（A）和第二部分（B）之间传送信息的第二部分（B）的第一部分（A）和信息终端（SB）。 连接（SC）具有晶体管电路，其具有第一部分（A）的至少一个晶体管（X），第二部分（B）的电阻（R1）和第一晶体管（E）），其中第一晶体管 （X）连接在第一部分（A）的基本电压（USS）和电阻（R1）之间，第二部分（B）的第一晶体管（E）连接在电阻（R1）和 第二部分（B）的电源电压（UDD1）。

公开(公告)号：US06928506B2

公开(公告)日：2005-08-09

申请号：US09747279

申请日：2000-12-21

申请人： Martin Czech ,  Michael Albert

发明人： Martin Czech ,  Michael Albert

IPC分类号： G06F13/40 ,  G06F13/14 ,  G11C11/24

CPC分类号： G06F13/4077

摘要： The invention relates to a circuit arrangement with two or more circuit sections, which cooperate through a data transfer device. The invention solves the problem of double area expenditure for two memory devices for each receiver, in that the data bus itself takes over the role of one of these memory devices, namely that of the memory device functioning as master. For this it is only necessary to integrate a single memory device on the data bus, which takes over the role of the no longer needed memory device for each data receiver. By saving the memory device associated with each receiver, the semiconductor chip area needed for communication buses can be optimized and the master memory device of the prior art may be replaced by the bus capacitance.

摘要翻译： 本发明涉及具有两个或多个电路部分的电路装置，其通过数据传送装置进行协作。 本发明解决了每个接收机的两个存储器件的双面积支出的问题，因为数据总线本身承担了这些存储器件之一的作用，即作为主器件的存储器件的作用。 为此，仅需要在数据总线上集成单个存储器件，其接管每个数据接收器不再需要的存储器件的作用。 通过保存与每个接收器相关联的存储器件，可以优化通信总线所需的半导体芯片面积，并且现有技术的主存储器件可以被总线电容代替。

公开(公告)号：US07202532B2

公开(公告)日：2007-04-10

申请号：US10761144

申请日：2004-01-20

申请人： Martin Czech ,  Erwe Reinhard

发明人： Martin Czech ,  Erwe Reinhard

IPC分类号： H01L23/62

CPC分类号： H01L27/0259

摘要： An integrated circuit includes at least two circuit components formed on a common semiconductor substrate. Each circuit component has a self-contained supply voltage system. Coupling circuits couple the supply voltage systems for the at least two circuit components. Each coupling circuit includes at least one transistor having a base formed by or within the substrate itself; more specifically, by or within a region of the substrate contiguous with collector doping zones and emitter doping zones of the transistor. The resistance between the transistor base and the potentials of the two supply voltage systems coupled by each of the coupling circuits is the intrinsic resistance of the substrate between the region forming the base and one of each contact doping zone conductively connected to the collector or emitter through a metallization applied to the substrate. To obtain an identical coupling behavior for the transistor in both directions, the collector and emitter of the transistor are preferably symmetrical, i.e., a transistor with a double emitter. The coupling circuit may be implemented with a single transistor, the dimensions of which are fixed by the desired volume resistivity. Greater flexibility of design with respect to accommodating the coupling circuit on one substrate surface without an increased area requirement is provided by employing multiple transistors as the coupling circuit. These transistors may be distributed independently of each other on the substrate surface.

摘要翻译： 集成电路包括形成在公共半导体衬底上的至少两个电路部件。 每个电路组件都具有独立的电源电压系统。 耦合电路耦合用于至少两个电路部件的电源电压系统。 每个耦合电路包括至少一个晶体管，其具有由衬底本身或衬底本身形成的基极; 更具体地说，在与晶体管的集电极掺杂区和发射极掺杂区相邻的衬底区域内或之内。 晶体管基极和由每个耦合电路耦合的两个电源电压系统的电位之间的电阻是在形成基极的区域和通过导电连接到集电极或发射极之间的每个接触掺杂区之一之间的衬底的固有电阻 施加到基底的金属化。 为了在两个方向上获得晶体管的相同耦合特性，晶体管的集电极和发射极优选是对称的，即具有双发射极的晶体管。 耦合电路可以用单个晶体管来实现，其尺寸被所需的体积电阻率固定。 通过采用多个晶体管作为耦合电路，提供了在不增加面积要求的情况下将耦合电路容纳在一个衬底表面上的更大的设计灵活性。 这些晶体管可以在衬底表面上彼此独立地分布。