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公开(公告)号：US20050187998A1
公开(公告)日：2005-08-25
申请号：US10783820
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
IPC分类号： G06F7/544 , G06F15/00 , H03K19/177
CPC分类号： G06F7/5443 , H03K19/17732
摘要： A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.
摘要翻译： 提供了一种可编程逻辑器件，其包括具有模式分离能力的MAC块。 可以同时实现不同的操作模式，从而可以在不同的操作模式之间分配MAC块的乘法器和其它DSP电路。 例如，可以使用一个乘法器来实现乘法模式，而另外两个乘法器可以用于实现两个乘法器模式的和。
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公开(公告)号：US20110161389A1
公开(公告)日：2011-06-30
申请号：US13042700
申请日：2011-03-08
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译： 可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。 在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。 在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。
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公开(公告)号：US09170775B2
公开(公告)日：2015-10-27
申请号：US12683686
申请日：2010-01-07
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译： 乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。 当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。 为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。 或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。
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公开(公告)号：US07930336B2
公开(公告)日：2011-04-19
申请号：US11566982
申请日：2006-12-05
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译： 可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。 在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。 在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。
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公开(公告)号：US20100169404A1
公开(公告)日：2010-07-01
申请号：US12683686
申请日：2010-01-07
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译： 乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。 当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。 为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。 或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。
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公开(公告)号：US20080133627A1
公开(公告)日：2008-06-05
申请号：US11566982
申请日：2006-12-05
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译： 可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。 在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。 在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。
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公开(公告)号：US08386553B1
公开(公告)日：2013-02-26
申请号：US11682787
申请日：2007-03-06
IPC分类号： G06F7/52
CPC分类号： G06F17/10 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.
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公开(公告)号：US07437401B2
公开(公告)日：2008-10-14
申请号：US10783820
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
IPC分类号： G06F7/48
CPC分类号： G06F7/5443 , H03K19/17732
摘要： A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.
摘要翻译： 提供了一种可编程逻辑器件，其包括具有模式分离能力的MAC块。 可以同时实现不同的操作模式，从而可以在不同的操作模式之间分配MAC块的乘法器和其它DSP电路。 例如，可以使用一个乘法器来实现乘法模式，而另外两个乘法器可以用于实现两个乘法器模式的和。
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公开(公告)号：US20050187997A1
公开(公告)日：2005-08-25
申请号：US10783789
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Hwang , Kumara Tharmalingam
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit. The least significant bits (LSBs) can be tied to ground and sent along the feedback path. To initialize the accumulator value, the MSBs of the initialization value can be input to the MAC block and sent directly to the add-subtract-accumulate unit. The LSBs can be sent to another multiplier that performs a multiply-by-one operation before being sent to the add-subtract-accumulate unit.
摘要翻译： 乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。 当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。 为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。 或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。 最低有效位（LSB）可以连接到地并沿反馈路径发送。 要初始化累加器值，初始化值的MSB可以输入到MAC块，并直接发送到加减法累加单元。 可以将LSB发送到另一个乘法器，该乘法器在发送到加减法累加单元之前执行乘法运算。
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公开(公告)号：US08788562B2
公开(公告)日：2014-07-22
申请号：US13042700
申请日：2011-03-08
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译： 可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。 在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。 在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。
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