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公开(公告)号：US08266199B2
公开(公告)日：2012-09-11
申请号：US11447472
申请日：2006-06-05
IPC分类号： G06F7/38
CPC分类号： H03K19/17732 , G06F7/527 , G06F7/5272
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
摘要翻译： 用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。 这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。 专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作。
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2.发明申请MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY 有权模块化数字信号处理电路，具有可选择的电路模块之间的专用连接公开(公告)号：US20100228806A1
公开(公告)日：2010-09-09
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lul , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lul , Suleyman Sirri Demirsoy , Hyun Yi
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。
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公开(公告)号：US20070185952A1
公开(公告)日：2007-08-09
申请号：US11447472
申请日：2006-06-05
IPC分类号： G06F7/00
CPC分类号： H03K19/17732 , G06F7/527 , G06F7/5272
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
摘要翻译： 用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。 这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。 专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作。
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4.发明授权Digital signal processing circuitry with redundancy and bidirectional data paths 有权具有冗余和双向数据路径的数字信号处理电路公开(公告)号：US08805916B2
公开(公告)日：2014-08-12
申请号：US12380841
申请日：2009-03-03
申请人： Martin Langhammer , Yi-Wen Lin , Keone Streicher
发明人： Martin Langhammer , Yi-Wen Lin , Keone Streicher
IPC分类号： G06F7/38 , G06F7/00 , G06F15/00 , H03K19/173 , H03K19/177 , H01L25/00 , H03K5/1252 , G06F7/53
CPC分类号： H03K5/1252 , G06F7/5324 , G06F2207/382 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect).
摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。
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5.发明授权Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry 有权模块化数字信号处理电路，具有电路模块之间任意可用的专用连接公开(公告)号：US08549055B2
公开(公告)日：2013-10-01
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。
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6.发明申请Digital signal processing circuitry with redundancy and bidirectional data paths 有权具有冗余和双向数据路径的数字信号处理电路公开(公告)号：US20100228807A1
公开(公告)日：2010-09-09
申请号：US12380841
申请日：2009-03-03
申请人： Martin Langhammer , Yi-Wen Lin , Keone Streicher
发明人： Martin Langhammer , Yi-Wen Lin , Keone Streicher
IPC分类号： G06F7/00
CPC分类号： H03K5/1252 , G06F7/5324 , G06F2207/382 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect).
摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。
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公开(公告)号：US08826038B1
公开(公告)日：2014-09-02
申请号：US13474745
申请日：2012-05-18
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： G06F21/00
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译： 阻止检测和擦除编码或加密密钥的电路，方法和装置。 这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。 本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。 在具体实施例中，使用第二密钥对第一密钥进行编码。 编码密钥用于对配置比特流或其他数据进行编码。 编码密钥存储在FPGA或其他设备上。 当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。 另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。 在存储之前可以进一步模糊编码密钥。
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公开(公告)号：US07818584B1
公开(公告)日：2010-10-19
申请号：US11042937
申请日：2005-01-25
CPC分类号： G06F12/1433 , G06F21/76 , H04L9/0894 , H04L2209/12 , H04L2209/16
摘要： Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.
摘要翻译： 存储和防止存储的编码密钥，串行标识号或其他信息的修改或擦除的电路，方法和装置。 与本发明的实施例一起存储的编码密钥可用于解码诸如FPGA的集成电路上的配置比特流。 序列号可用于跟踪或认证集成电路。 本发明的实施例将该信息存储在诸如SRAM，DRAM，EPROM，EEPROM，闪存，熔丝阵列或其它类型的存储器之类的存储器中。 为了防止其擦除或修改，存储器的写使能电路然后被永久禁用，并且如果存储器是易失性的，则提供连续的电源。 进一步细化验证在允许设备被配置或可操作之前写使能电路已被禁用。
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公开(公告)号：US08433930B1
公开(公告)日：2013-04-30
申请号：US12884753
申请日：2010-09-17
IPC分类号： H04L29/06
CPC分类号： G06F12/1433 , G06F21/76 , H04L9/0894 , H04L2209/12 , H04L2209/16
摘要： Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.
摘要翻译： 存储和防止存储的编码密钥，串行识别号码或其他信息的修改或擦除的电路，方法和装置。 与本发明的实施例一起存储的编码密钥可用于解码诸如FPGA的集成电路上的配置比特流。 序列号可用于跟踪或认证集成电路。 本发明的实施例将该信息存储在诸如SRAM，DRAM，EPROM，EEPROM，闪存，熔丝阵列或其它类型的存储器之类的存储器中。 为了防止其擦除或修改，存储器的写使能电路然后被永久禁用，并且如果存储器是易失性的，则提供连续的电源。 进一步细化验证在允许设备被配置或可操作之前写使能电路已被禁用。
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公开(公告)号：US07836117B1
公开(公告)日：2010-11-16
申请号：US11458361
申请日：2006-07-18
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , G06F5/01 , G06F7/4812 , G06F7/49921 , G06F7/49963 , G06F7/5443 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/1737
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
摘要翻译： 用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。 这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。 专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作。
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