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公开(公告)号：US20220244767A1
公开(公告)日：2022-08-04
申请号：US17726924
申请日：2022-04-22
申请人： Marvell Asia Pte Ltd
发明人： Avinash Sodani , Srinivas Sripada , Ramacharan Sundararaman , Chia-Hsin Chen , Nikhil Jayakumar
摘要： A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.
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公开(公告)号：US11789513B1
公开(公告)日：2023-10-17
申请号：US17827508
申请日：2022-05-27
申请人： Marvell Asia Pte Ltd
发明人： Atul Bhattarai , Srinivas Sripada , Avinash Sodani , Michael Dudek , Darren Walworth , Roshan Fernando , James Irvine , Mani Gopal
IPC分类号： G06F1/3206 , G06F11/30
CPC分类号： G06F1/3206 , G06F11/3062
摘要： A system includes a multicore chip configured to perform machine learning (ML) operations. The system also includes a power monitoring module configured to measure power consumption of the multicore chip on a main power rail of the multicore chip. The power monitoring module is further configured to assert a signal in response to the measured power consumption exceeding a first threshold. The power monitoring module is further configured to transmit the asserted signal to a power throttling module to initiate a power throttling for the multicore chip.
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公开(公告)号：US11526204B2
公开(公告)日：2022-12-13
申请号：US17508845
申请日：2021-10-22
申请人： Marvell Asia Pte Ltd
IPC分类号： G06F1/32 , G06F1/08 , G06F1/3287
摘要： A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.
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公开(公告)号：US11181967B2
公开(公告)日：2021-11-23
申请号：US16947445
申请日：2020-07-31
IPC分类号： G06F1/32 , G06F1/08 , G06F1/3287
摘要： A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.
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公开(公告)号：US11994925B2
公开(公告)日：2024-05-28
申请号：US16947446
申请日：2020-07-31
IPC分类号： G06F1/3203 , G06F1/08 , G06F1/10 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/3293
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/10
摘要： A system includes a first and a second group of cores in a multicore system. Each core of the first/second group is configured to process data. Each core within the first/second group is configured to enter into an idle state in response to being idle for a first/second period of time respectively. Every idle core in the first/second group is configured to transition out of the idle state and into an operational mode in response to receiving a signal having a first/second value respectively and further in response to having a pending operation to process.
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公开(公告)号：US11340673B1
公开(公告)日：2022-05-24
申请号：US16864076
申请日：2020-04-30
发明人： Avinash Sodani , Srinivas Sripada , Ramacharan Sundararaman , Chia-Hsin Chen , Nikhil Jayakumar
摘要： A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.
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公开(公告)号：US11687136B2
公开(公告)日：2023-06-27
申请号：US17726924
申请日：2022-04-22
申请人： Marvell Asia Pte Ltd
发明人： Avinash Sodani , Srinivas Sripada , Ramacharan Sundararaman , Chia-Hsin Chen , Nikhil Jayakumar
摘要： A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.
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公开(公告)号：US11507170B1
公开(公告)日：2022-11-22
申请号：US17086264
申请日：2020-10-30
发明人： Atul Bhattarai , Srinivas Sripada , Avinash Sodani , Michael Dudek , Darren Walworth , Roshan Fernando , James Irvine , Mani Gopal
IPC分类号： G06F1/3206 , G06F11/30
摘要： A system includes a multicore chip configured to perform machine learning (ML) operations. The system also includes a power monitoring module configured to measure power consumption of the multicore chip on a main power rail of the multicore chip. The power monitoring module is further configured to assert a signal in response to the measured power consumption exceeding a first threshold. The power monitoring module is further configured to transmit the asserted signal to a power throttling module to initiate a power throttling for the multicore chip.
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公开(公告)号：US20210318740A1
公开(公告)日：2021-10-14
申请号：US16947446
申请日：2020-07-31
IPC分类号： G06F1/3203 , G06F1/10 , G06F1/08
摘要： A system includes a first and a second group of cores in a multicore system. Each core of the first/second group is configured to process data. Each core within the first/second group is configured to enter into an idle state in response to being idle for a first/second period of time respectively. Every idle core in the first/second group is configured to transition out of the idle state and into an operational mode in response to receiving a signal having a first/second value respectively and further in response to having a pending operation to process.
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