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公开(公告)号：US11635739B1
公开(公告)日：2023-04-25
申请号：US16864085
申请日：2020-04-30
IPC分类号： G06F1/32 , G05B19/042 , G06N20/00 , G06F1/3206
摘要： A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.
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2.发明授权公开(公告)号：US11586446B1
公开(公告)日：2023-02-21
申请号：US17325433
申请日：2021-05-20
IPC分类号： G06F9/4401 , G06F9/445 , G06F13/42 , G06F13/40 , G06F9/30
摘要： A new approach is proposed to support hardware-based PCIe link up based on post silicon characterization of an electronic device. A non-volatile storage medium of a bootup unit on the electronic device maintains an initialization sequence for the physical layer of a PCIe link, and a non-volatile storage medium allows flexible programming. During operation, the bootup unit reads from the non-volatile storage medium instructions to program/override one or more PCIe physical layer settings and controller registers for the PCIe link based on the post silicon characterization of the electronic device. The bootup unit is limited to access and override only to the one or more physical layer settings and controller registers of the PCIe link. The entire process of reading the initialization sequence and programming the one or more PCIe physical layer settings and the controller registers happens within time limit constraints of the PCIe specification for latency reduction.
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公开(公告)号：US20210389884A1
公开(公告)日：2021-12-16
申请号：US17162046
申请日：2021-01-29
IPC分类号： G06F3/06
摘要： A new approach is proposed to support hardware-based memory region protection for an electronic device. One or more sources/requesting access to a memory/storage that is local to or associated with the electronic device are categorized into at least two types—a set of trusted sources and a set of untrusted sources. Accordingly, a memory manager is configured to partition the memory into a plurality of regions including at least a secure region that is accessible only by a trusted source and a non-secure region that is accessible by an untrusted source. Any access attempt to the secure region by one of the untrusted sources will be blocked. During operation, the memory manager is configured to dynamically adjust the demarcation and/or size of the secure region and the non-secure region of the memory via remapping of the memory based on current access need to data maintained in the memory.
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公开(公告)号：US11687136B2
公开(公告)日：2023-06-27
申请号：US17726924
申请日：2022-04-22
申请人： Marvell Asia Pte Ltd
发明人： Avinash Sodani , Srinivas Sripada , Ramacharan Sundararaman , Chia-Hsin Chen , Nikhil Jayakumar
摘要： A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.
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5.发明授权公开(公告)号：US11836501B1
公开(公告)日：2023-12-05
申请号：US18098388
申请日：2023-01-18
申请人： Marvell Asia Pte Ltd
IPC分类号： G06F9/4401 , G06F9/445 , G06F9/30 , G06F13/40 , G06F13/42
CPC分类号： G06F9/4406 , G06F9/30054 , G06F9/44505 , G06F13/409 , G06F13/4221 , G06F2213/0026
摘要： A new approach is proposed to support hardware-based PCIe link up based on post silicon characterization of an electronic device. A non-volatile storage medium of a bootup unit on the electronic device maintains an initialization sequence for the physical layer of a PCIe link, and a non-volatile storage medium allows flexible programming. During operation, the bootup unit reads from the non-volatile storage medium instructions to program/override one or more PCIe physical layer settings and controller registers for the PCIe link based on the post silicon characterization of the electronic device. The bootup unit is limited to access and override only to the one or more physical layer settings and controller registers of the PCIe link. The entire process of reading the initialization sequence and programming the one or more PCIe physical layer settings and the controller registers happens within time limit constraints of the PCIe specification for latency reduction.
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公开(公告)号：US11829492B1
公开(公告)日：2023-11-28
申请号：US17162521
申请日：2021-01-29
CPC分类号： G06F21/62
摘要： A new approach is proposed to support hardware-based protection for registers of an electronic device. Sources requesting access to the registers are categorized into a set of internal sources that can be trusted and a set of external sources that are untrusted. The registers are classified into a set of internal registers allowed to be accessed by the internal resources only, a set of read-only external registers that can be read by the external resources in addition to accessed by the internal resources, and a set of read/write external registers that can be read and written by both the internal and the external resources. Each access request by a source to the registers includes the source type, wherein access request is granted or denied based on the matching between the source bits in the access request and the register classification bits of the one or more registers to be accessed.
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公开(公告)号：US20220244767A1
公开(公告)日：2022-08-04
申请号：US17726924
申请日：2022-04-22
申请人： Marvell Asia Pte Ltd
发明人： Avinash Sodani , Srinivas Sripada , Ramacharan Sundararaman , Chia-Hsin Chen , Nikhil Jayakumar
摘要： A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.
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公开(公告)号：US10929778B1
公开(公告)日：2021-02-23
申请号：US16420078
申请日：2019-05-22
IPC分类号： G06F9/32 , G06F15/76 , G06F15/80 , G06F12/00 , G06N3/04 , G06N20/00 , G06F12/06 , G06F15/78 , G06F15/17 , G06F12/0846 , G06F9/38
摘要： A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.
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公开(公告)号：US11868475B1
公开(公告)日：2024-01-09
申请号：US17086371
申请日：2020-10-31
发明人： Ramacharan Sundararaman , Nithyananda Miyar , Martin Kovac , Avinash Sodani , Raghuveer Shivaraj
IPC分类号： G06F21/57 , G06F9/4401
CPC分类号： G06F21/575 , G06F9/4401
摘要： A new approach is proposed that contemplates systems and methods to support post reset fuse reload for latency reduction. First, values of fuses are read once and stored into one or more load registers on an electronic device, wherein the load registers are protected. Once the values of the fuse are loaded into the load registers, a valid indicator of the load registers is set indicating that the values have been successfully loaded into the load registers. When other components of the electronic device need to access these values, the other components will check the load registers first. If it is determined that the valid indicator of the load registers is set, the stored values are read from the load registers instead of from the fuses. If the valid indicator of the load registers is not set, the values are loaded again from the fuses into the load registers.
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公开(公告)号：US11734608B2
公开(公告)日：2023-08-22
申请号：US17247810
申请日：2020-12-23
CPC分类号： G06N20/00 , G06F12/0607 , G06F9/3895 , G06F9/3897 , G06F12/0851 , G06F15/17 , G06F15/781 , G06F15/7807 , G06F15/7857 , G06F15/80 , G06F2212/1041
摘要： A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.
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