-
公开(公告)号:US08839016B2
公开(公告)日:2014-09-16
申请号:US13683056
申请日:2012-11-21
Applicant: Marvell World Trade Ltd.
Inventor: Zhenyu Zhang , James Kang-Wuu Jan , Frank Huang , Yong Jiang , Yui Lin , Lite Lo
CPC classification number: G06F1/324 , G06F1/3203 , G06F1/3253 , G06F13/385 , Y02D10/151 , Y02D50/20
Abstract: USB self-idling techniques are described. In one or more embodiments, a Universal Serial Bus (USB) device comprises one or more modules to communicate via USB and self-idle by presenting an idle mode to a USB host and entering a suspend mode after the idle mode, the suspend mode being entered while the USB host is presented with the idle mode.
Abstract translation: 描述USB自怠速技术。 在一个或多个实施例中,通用串行总线(USB)设备包括一个或多个模块,以通过USB空闲模式向USB主机呈现空闲模式并在空闲模式之后进入挂起模式,通过USB和自我空闲进行通信,挂起模式为 在USB主机呈现空闲模式时输入。
-
公开(公告)号:US20130346777A1
公开(公告)日:2013-12-26
申请号:US13683056
申请日:2012-11-21
Applicant: MARVELL WORLD TRADE LTD.
Inventor: Zhenyu Zhang , James Kang-Wuu Jan , Frank Huang , Yong Jiang , Yui Lin , Lite Lo
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3203 , G06F1/3253 , G06F13/385 , Y02D10/151 , Y02D50/20
Abstract: USB self-idling techniques are described. In one or more embodiments, a Universal Serial Bus (USB) device comprises one or more modules to communicate via USB and self-idle by presenting an idle mode to a USB host and entering a suspend mode after the idle mode, the suspend mode being entered while the USB host is presented with the idle mode.
Abstract translation: 描述USB自怠速技术。 在一个或多个实施例中,通用串行总线(USB)设备包括一个或多个模块,以通过USB空闲模式向USB主机呈现空闲模式并在空闲模式之后进入挂起模式,通过USB和自我空闲进行通信,挂起模式为 在USB主机呈现空闲模式时输入。
-
公开(公告)号:US20170099063A1
公开(公告)日:2017-04-06
申请号:US15266458
申请日:2016-09-15
Applicant: Marvell World Trade Ltd.
Inventor: Vijay Ganwani , Vijay Ahirwar , Yui Lin , Sudhir Srinivasa , Hongyuan Zhang , Sridhar Narravula
CPC classification number: H03M3/378 , H03M1/1085 , H03M1/1095 , H03M3/356 , H04B1/1036 , H04B2001/1063 , H04L7/0331 , H04L27/2636
Abstract: Apparatus for determining a signal-to-quantization-noise ratio of a quantization circuit includes a signal generator that generates an input test signal for input to the quantization circuit, circuitry for isolating, from output of the quantization circuit, a signal representing quantization noise, and circuitry for determining a ratio of the output of the quantization circuit to the signal representing quantization noise. The signal generator generates an analog test tone having a frequency, and the circuitry for isolating includes a notch filter filtering that frequency. Alternatively, the circuitry for isolating includes circuitry for generating a digital test signal, and a digital subtractor for subtracting the digital test signal from the output of the quantization circuit. According to another alternative, the circuitry for isolating includes a transformation circuit whose outputs represent a peak of the output of the quantization circuit and a noise floor of the output of the quantization circuit.
-
-