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公开(公告)号：US07205615B2
公开(公告)日：2007-04-17
申请号：US10859219
申请日：2004-06-03
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。
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公开(公告)号：US07893501B2
公开(公告)日：2011-02-22
申请号：US12170191
申请日：2008-07-09
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。
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公开(公告)号：US07417289B2
公开(公告)日：2008-08-26
申请号：US11730988
申请日：2007-04-05
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。
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公开(公告)号：US08383486B2
公开(公告)日：2013-02-26
申请号：US13486877
申请日：2012-06-01
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。
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公开(公告)号：US08203186B2
公开(公告)日：2012-06-19
申请号：US12985636
申请日：2011-01-06
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。
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公开(公告)号：US20070194388A1
公开(公告)日：2007-08-23
申请号：US11730988
申请日：2007-04-05
IPC分类号： H01L29/94
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the NMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在NMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。
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公开(公告)号：US20090050981A1
公开(公告)日：2009-02-26
申请号：US12170191
申请日：2008-07-09
IPC分类号： H01L47/00
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。
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公开(公告)号：US08354726B2
公开(公告)日：2013-01-15
申请号：US11798528
申请日：2007-05-15
申请人： Masafumi Tsutsui
发明人： Masafumi Tsutsui
IPC分类号： H01L29/76
CPC分类号： H01L21/823412 , H01L21/823468 , H01L21/823481 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device includes: a first active region surrounded with an isolation region of a semiconductor substrate; a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region; a first side-wall insulating film; an auxiliary pattern formed to be spaced apart in the gate width direction from the protrusion of the first gate electrode; a second side-wall insulating film; and a stress-containing insulating film containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film. In this device, the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of: the sum of the thicknesses of the first and second side-wall insulating films; and the double of the thickness of the stress-containing insulating film.
摘要翻译： 半导体器件包括：被半导体衬底的隔离区包围的第一有源区; 第一栅电极，形成在所述第一有源区上并具有在所述隔离区上突出的突起; 第一侧壁绝缘膜; 辅助图案形成为在栅极宽度方向上与第一栅电极的突起间隔开; 第二侧壁绝缘膜; 以及含有内应力的含应力的绝缘膜，形成为覆盖第一栅电极，第一侧壁绝缘膜，辅助图案和第二侧壁绝缘膜。 在该装置中，第一栅电极和辅助图案之间的距离小于第一和第二侧壁绝缘膜的厚度之和的总和; 并且是含应力的绝缘膜的厚度的两倍。
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公开(公告)号：US08265054B2
公开(公告)日：2012-09-11
申请号：US12613002
申请日：2009-11-05
申请人： Masafumi Tsutsui
发明人： Masafumi Tsutsui
IPC分类号： H04B7/216
CPC分类号： H01Q3/2605 , H01Q1/246 , H01Q3/267 , H04B7/0617 , H04B7/0639 , H04L25/0204 , H04L25/03343 , H04L2025/03426 , H04L2025/03802
摘要： A wireless communication apparatus of a base station uses antennas for multiple systems, forms a multi-beam, transmits data to a mobile station, and includes a code book configured to store therein beamforming information; a pre-coder that reads the code book and executes a process of forming a given beam for the data; a control unit that, based on feedback information to correct variations in phase occurring at transmitting circuits respectively corresponding to each of the systems, performs control such that the beamforming information to correct the variations in phase is read from the code book; and a phase correcting unit that corrects a phase of the multi-beam formed by the pre-coder, based on the feedback information and such that relations among the phases of the multi-beam become substantially linear.
摘要翻译： 基站的无线通信装置使用多个系统的天线，形成多波束，向移动台发送数据，并且包括配置为在其中存储波束成形信息的码本; 读取代码簿并执行为数据形成给定波束的处理的预编码器; 控制单元，其基于反馈信息来校正发生在与每个系统相对应的发射电路处的相位变化，执行控制，使得从码本中读取纠正相位变化的波束成形信息; 以及相位校正单元，其基于反馈信息校正由预编码器形成的多波束的相位，并且使得多波束的相位之间的关系变得基本上线性。
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公开(公告)号：US20110073954A1
公开(公告)日：2011-03-31
申请号：US12961168
申请日：2010-12-06
IPC分类号： H01L27/092
CPC分类号： H01L21/823462 , H01L21/823493 , H01L27/11
摘要： In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.
摘要翻译： 在第一部分的半导体衬底中，形成在半导体衬底的内部具有杂质浓度峰值的沟道区，在第二部分和第三部分的半导体衬底中，在 形成靠近基板表面的位置。 然后，在第一部分，第二部分和第三部分中形成延伸区域。 之后，对基板进行热处理以消除延伸区域中产生的缺陷。 然后，使用栅电极和侧壁间隔物作为掩模，在第一部分，第二部分和第三部分中形成源极/漏极区域。
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