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公开(公告)号：US4228430A
公开(公告)日：1980-10-14
申请号：US860117
申请日：1977-12-13
摘要： Disclosed is a raster scanning type CRT display apparatus having a microprogrammed processor for primarily controlling the input and output of data to and from an external information source. This CRT display apparatus comprises a plurality of cursor controlling registers having their contents set by the processor. The contents of these registers define the configuration of a cursor for displaying a data entry position on its screen, the decision with respect to the blinking of the cursor, and a period of the blinking.
摘要翻译： 公开了一种光栅扫描型CRT显示装置，其具有微程序处理器，用于主要控制与外部信息源的数据的输入和输出。 该CRT显示装置包括多个光标控制寄存器，其具有由处理器设置的内容。 这些寄存器的内容定义了用于在其屏幕上显示数据输入位置的光标的配置，关于光标的闪烁的决定以及闪烁的周期。
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公开(公告)号：US4149264A
公开(公告)日：1979-04-10
申请号：US802463
申请日：1977-06-01
申请人： Nagaharu Hamada , Masahiro Iwamura
发明人： Nagaharu Hamada , Masahiro Iwamura
CPC分类号： G09G5/18
摘要： Disclosed is a CRT display apparatus of a raster scanning type which includes a microprocessor as a unit for data handling or processing in an input/output control part for controlling data transfer with a computer and/or keyboard, the operations of the microprocessor being controlled by a microprogram stored in a microprogram memory. A timing control unit or part for producing various timing signals for controlling displays is connected to the microprocessor through a data bus and an address bus so that control parameter for the various timing operations can be set through the microprogram. The timing control part comprises programmable control registers, counters for generating timing signals and coincidence detectors or comparators for detecting coincidence between the outputs from the control registers and the timing signals from the associated counters.
摘要翻译： 公开了一种光栅扫描型的CRT显示装置，其包括微处理器作为用于通过计算机和/或键盘控制数据传输的输入/输出控制部分中的数据处理或处理的单元，微处理器的操作由 存储在微程序存储器中的微程序。 用于产生用于控制显示器的各种定时信号的定时控制单元或部件通过数据总线和地址总线连接到微处理器，使得可以通过微程序设置各种定时操作的控制参数。 定时控制部分包括可编程控制寄存器，用于产生定时信号的计数器和用于检测来自控制寄存器的输出与来自关联计数器的定时信号之间的一致性的重合检测器或比较器。
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3.发明授权
公开(公告)号：US4129859A
公开(公告)日：1978-12-12
申请号：US766728
申请日：1977-02-08
申请人： Masahiro Iwamura , Nagaharu Hamada , Toshitaka Hara , Nobuo Sato
发明人： Masahiro Iwamura , Nagaharu Hamada , Toshitaka Hara , Nobuo Sato
CPC分类号： G09G5/343
摘要： A raster scan type CRT display system is disclosed which has a randomly accessable refresh memory. The display system comprises column and row start address registers for defining a read start address for the refresh memory, column and row address counters for counting the contents of the column and row start address registers as start positions to generate a read address of the refresh memory for display, column and row cursor registors for defining a data entry position on a CRT screen, and column and row address generators for generating an entry address for the refresh memory based on the contents of the column and row start address registers and the contents of the column and row cursor registers, whereby a rolling or shifting of the image is effected and the refresh memory can be accessed by a processor for read/write operation without the need to monitor the image rolling.
摘要翻译： 公开了一种具有随机存取的刷新存储器的光栅扫描型CRT显示系统。 显示系统包括用于定义刷新存储器的读起始地址的列和行起始地址寄存器，用于对列的内容进行计数的列和行地址计数器以及行起始地址寄存器作为起始位置，以生成刷新存储器的读地址 用于在CRT屏幕上定义数据输入位置的显示器，列和行光标注册器，以及用于根据列和行起始地址寄存器的内容产生刷新存储器的入口地址的列和行地址生成器， 列和行光标寄存器，从而影响图像的滚动或移位，并且可以由处理器访问刷新存储器以进行读/写操作，而不需要监视图像滚动。
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公开(公告)号：US3997891A
公开(公告)日：1976-12-14
申请号：US583408
申请日：1975-06-03
CPC分类号： G06F3/0383
摘要： A light pen detection system used for a display system using a cathode ray tube (CRT) in which the operation for detecting the character display position on the CRT face is started when the operation switch of the light pen is turned on, and repeatedly progresses in synchronism with the picture repetition rate, and when a position marker is displayed at the character display position detected through such detecting operation, the operation switch of the light pen is turned off thereby to stop such detecting operation, whereby the character display position detected is obtained as the up-to-date one indicated by the light pen.
摘要翻译： 一种用于使用阴极射线管（CRT）的显示系统的光笔检测系统，其中当光笔的操作开关接通时，开始用于检测CRT面上的字符显示位置的操作，并重复进行 与图像重复率同步，并且当通过这种检测操作检测到的字符显示位置处显示位置标记时，关闭光笔的操作开关，从而停止这种检测操作，由此获得检测到的字符显示位置 作为由光笔指示的最新的。
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5.发明授权Magnetic-field-angle measurement apparatus and rotational-angle measurement apparatus using same 有权磁场角测量装置和使用其的旋转角度测量装置公开(公告)号：US09506997B2
公开(公告)日：2016-11-29
申请号：US13697690
申请日：2010-05-14
摘要： In a magnetic-field angle detection device and a rotation angle detection device in which the accuracy of the measured angle is not degraded even if the MR ratio of the tunneling magnetoresistance element is increased. In a magnetic-field-angle measurement apparatus including a magnetic-field-angle detection circuit and a magnetic sensor having a tunneling magnetoresistance element with a pinned magnetic layer, the magnetic-field-angle detection circuit has a power-supply unit that outputs a constant voltage as a bias voltage to the tunneling magnetoresistance element of the magnetic sensor and a current-detection unit that detects an output current of the tunneling magnetoresistance element. The accuracy of the measured angle of the magnetic-field angle detection device and the rotation angle detection device is improved by measuring the tunneling magnetoresistance element current while maintaining the terminal voltage of the tunneling magnetoresistance element constant with input impedance of the current-detection unit as zero.
摘要翻译： 在磁场角检测装置和旋转角度检测装置中，即使隧道磁阻元件的MR比增加，测量角度的精度也不会降低。 在包括磁场角检测电路的磁场角测量装置和具有钉扎磁性层的隧道磁阻元件的磁传感器中，磁场角检测电路具有电源单元，其输出 恒定电压作为磁传感器的隧道磁阻元件的偏置电压，以及电流检测单元，其检测隧道磁阻元件的输出电流。 通过测量隧道磁阻元件电流来改善磁场角检测装置和旋转角度检测装置的测量角度的精度，同时保持隧道磁阻元件的端电压恒定，电流检测单元的输入阻抗为 零。
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6.发明申请公开(公告)号：US20060158162A1
公开(公告)日：2006-07-20
申请号：US11206225
申请日：2005-08-18
CPC分类号： H02M7/219 , H02P9/30 , H02P2101/45
摘要： V-phase upper-arm open phase detecting circuit outputs a permission signal to allow U-phase lower-arm MOSFET to be conductive when the V-phase voltage is higher than the positive electrode potential. In response to this permission signal, U-phase lower-arm driver circuit drives U-phase lower-arm MOSFET. V-phase lower-arm open phase detecting circuit outputs a permission signal to allow U-phase upper-arm MOSFET to be conductive when the V-phase voltage is lower than the negative electrode potential. In response to this permission signal, U-phase upper-arm driver circuit drives U-phase upper-arm MOSFET. Thereby, a MOS rectifying device capable of rectifying even when an open phase occurs, a driving method thereof, and a motor vehicle using thereof can be provided.
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7.发明授权Method and apparatus for driving a semiconductor element with variable resistance circuitry 失效用可变电阻电路驱动半导体元件的方法和装置公开(公告)号：US06275399B1
公开(公告)日：2001-08-14
申请号：US09654892
申请日：2000-09-05
申请人： Hideki Miyazaki , Katsunori Suzuki , Koji Tateno , Junichi Sakano , Masahiro Iwamura , Mutsuhiro Mori
发明人： Hideki Miyazaki , Katsunori Suzuki , Koji Tateno , Junichi Sakano , Masahiro Iwamura , Mutsuhiro Mori
IPC分类号： H02M768
CPC分类号： H03K17/0822 , H03K17/165
摘要： In a driving apparatus of a power semiconductor element for conducting or interrupting a main current, first resistance variable for changing a first resistance according to a control voltage, and second resistance variable for changing a second resistance according to a voltage between a first and a second terminal are provided, and either one of a voltage of a control power supply or a voltage between the first and the second terminal is voltage-divided by the first resistance and the second resistance, and the divided voltage is applied to a control gate terminal at the time of conducting or interrupting the main current.
摘要翻译： 在用于导通或中断主电流的功率半导体元件的驱动装置中，根据控制电压改变第一电阻的第一电阻变量，以及根据第一和第二电压之间的电压来改变第二电阻的第二电阻变量 端子，并且控制电源的电压或第一和第二端子之间的电压中的任一个被第一电阻和第二电阻分压，并且分压被施加到控制栅极端子 执行或中断主电流的时间。
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8.发明授权Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory 失效根据程序的并行性通过使用高速缓冲存储器来处理多种模式的数据的方法和装置
公开(公告)号：US5968160A
公开(公告)日：1999-10-19
申请号：US923632
申请日：1997-09-04
申请人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
发明人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
CPC分类号： G06F9/3891 , G06F12/084 , G06F15/17381 , G06F15/8015 , G06F9/30087 , G06F9/3009 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3885
摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.
摘要翻译： 具有应对程序的并行性的灵活性的数据处理系统包括用于执行指令的多个处理器元件，由多个处理器元件共享的主存储器和用于使多个处理器元件能够操作的多个并行操作控制设备 同步。 分别对应于多个处理器元件提供多个并行操作控制设备。 数据处理系统还包括多处理器操作控制设备，用于使多个处理器元件能够独立地操作，以及用于保持指示并行操作模式或多处理器模式中的哪一个被激活的值的标志。 共享高速缓冲存储器以空白指令实现并由高速缓存控制器控制，从而消除了存储在高速缓冲存储器中的数据的不一致性。
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公开(公告)号：US5742551A
公开(公告)日：1998-04-21
申请号：US463851
申请日：1995-06-05
CPC分类号： H03F3/72 , H03K17/6264 , H03F2203/7203
摘要： A constant current source is connected in series to a current source circuit including a MOS transistor which is used as a current source for a differential output amplifier circuit, an emitter follower circuit or a source follower circuit used with a semiconductor integrated circuit. In a multiplex circuit, an input signal is inputted to each of base terminals of a plurality of bipolar transistors. When one input signal is selected, the bipolar transistor corresponding to the selected input signal is made to be operable with an input signal from a signal input terminal by a control circuit. The bipolar transistors corresponding to the non-selection input signals are turned OFF irrespective of potential levels of the individual input signals by current drawing circuits. There is also disclosed a semiconductor memory circuit having a plurality of memory cells, a memory cell selection scheme and a sense amplifier for amplifying data outputted from the selected memory cell, in which a constant current circuit is provided in series connection to the sense amplifier to enhance the performance characteristics of the memory circuit. Also, a plural memory array scheme is disclosed which employs multiplexing techniques connected to presense amplifier circuits of the respective memory arrays.
摘要翻译： 恒流源串联连接到电流源电路，该电流源电路包括用作差分输出放大器电路的电流源的MOS晶体管，射极跟随器电路或与半导体集成电路一起使用的源极跟随器电路。 在复用电路中，输入信号被输入到多个双极晶体管的每个基极端子。 当选择一个输入信号时，与所选择的输入信号相对应的双极晶体管可以通过控制电路与来自信号输入端的输入信号一起工作。 对应于非选择输入信号的双极晶体管截止，而与当前绘图电路的各个输入信号的电位电平无关。 还公开了具有多个存储单元的半导体存储器电路，存储单元选择方案和用于放大从所选择的存储单元输出的数据的读出放大器，其中恒定电流电路与读出放大器串联连接， 提高存储电路的性能特点。 此外，公开了一种多重存储器阵列方案，其采用连接到相应存储器阵列的预放大器电路的复用技术。
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公开(公告)号：US5657264A
公开(公告)日：1997-08-12
申请号：US159256
申请日：1993-11-30
IPC分类号： G11C7/12 , G11C11/419 , G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.
摘要翻译： 半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。 写驱动器包括第一组的MOSFET和第二组的MOSFET。 在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。 另一方面，第二组的MOSFET通常处于OFF状态。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平 数据线到低电平。
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