公开(公告)号：US4699640A

公开(公告)日：1987-10-13

申请号：US885857

申请日：1986-07-14

申请人： Masami Suzuki ,  Kouki Yamaguchi ,  Hisato Katayama ,  Tadayoshi Muta ,  Masakuni Okubo ,  Akira Mochizuki ,  Hiroshi Adachi

发明人： Masami Suzuki ,  Kouki Yamaguchi ,  Hisato Katayama ,  Tadayoshi Muta ,  Masakuni Okubo ,  Akira Mochizuki ,  Hiroshi Adachi

IPC分类号： F24F7/06 ,  F24F3/16 ,  F24F7/10 ,  B01D50/00

CPC分类号： F24F3/161 ,  F24F7/10

摘要： A clean room is adapted to provide a plurality of clean air zones with different degrees of cleanliness. Air is passed through high efficiency particulate air filters in the ceiling of the room and withdrawn through shutters in the floor of the room. The shutters are adjustable to maintain a pressure-balanced system. The room is divided by walls and partitions to define different zones which are filtered by different classes of filters depending on the degree of cleanliness required in each zone.

摘要翻译： 洁净室适于提供具有不同清洁度的多个清洁空气区域。 空气通过房间天花板中的高效颗粒空气过滤器，并通过房间地板上的快门取出。 百叶窗是可调节的，以保持压力平衡系统。 房间由墙壁和隔板分隔，以根据每个区域所需的清洁度确定不同类别的过滤器的不同区域。

公开(公告)号：US20110147941A1

公开(公告)日：2011-06-23

申请号：US13059720

申请日：2009-10-19

申请人： Tadayoshi Muta

发明人： Tadayoshi Muta

IPC分类号： H01L23/532 ,  H01L21/60

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13144 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. A first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.

摘要翻译： 具有高纵横比的穿透电极的半导体装置通过低温处理制造。 分别设置在前表面侧和后表面侧的半导体衬底1的第一电极3和第二电极6通过填充在接触孔4中的导电体7和第二电极的延伸部6a电连接 尽管接触孔4具有高纵横比，但是通过使用导电物体7可以实现使用低温处理的成膜，而不是在第二电极6的底部形成第二电极6 接触孔4。

公开(公告)号：US06702413B2

公开(公告)日：2004-03-09

申请号：US09987504

申请日：2001-11-15

申请人： Hiroshi Takabayashi ,  Tadayoshi Muta ,  Toru Yamane

发明人： Hiroshi Takabayashi ,  Tadayoshi Muta ,  Toru Yamane

IPC分类号： B41J25308

CPC分类号： B41J2/14072 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322

摘要： A liquid discharge head which comprises an element substrate having on one surface thereof energy generating element for generating energy to be utilized for discharging liquid from a liquid discharge port, and a liquid supply port communicated with the liquid discharge port, a printed substrate provided with an external fetch electrode, and an IC component for control use for the energy generating element having provided therefor an output side electrode connected with the energy generating element and an input side electrode connected with the external fetch electrode. For this liquid discharge head, at least the aforesaid output side electrode of the IC component for control use is provided for the one surface of the element substrate. With the structure thus arranged, it is made easier to elongate the liquid discharge head in higher precision, and also, as compared with the case where the driver (driving element) for the discharge energy generating element is incorporated on the assembling substrate, the nondefective ratio of the finished products thereof is enhanced, hence contributing to the manufacture at lower costs.

摘要翻译： 一种液体排出头，包括：元件基板，其一个表面上具有用于产生用于从液体排出口排出液体的能量的能量产生元件和与液体排出口连通的液体供给口;印刷基板， 外部提取电极和用于能量产生元件的控制用IC集成电路，其设置有与能量产生元件连接的输出侧电极和与外部取出电极连接的输入侧电极。 对于该液体排出头，至少在元件基板的一个表面上设置用于控制用的IC部件的上述输出侧电极。 利用如此布置的结构，更容易以更高的精度使液体排出头细长化，并且与将组装衬底上的排出能量产生元件的驱动器（驱动元件）相结合的情况相比，无缺陷 其成品的比例提高，从而以较低的成本有助于制造。

公开(公告)号：US20110006303A1

公开(公告)日：2011-01-13

申请号：US12922530

申请日：2009-03-17

申请人： Tadayoshi Muta

发明人： Tadayoshi Muta

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： G01R31/2853 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2924/09701 ,  H01L2924/12044

摘要： Provided is a semiconductor apparatus which may check a state of connection of a penetrating electrode in a semiconductor substrate with ease. A semiconductor apparatus manufacturing method includes: forming in a semiconductor substrate at least three kinds of the through-holes each having a large area, a middle area, and a small area of openings; forming a conductive layer on an inner surface of the at least three kinds of the through-holes having different areas of the openings to form the penetrating electrodes; and measuring resistance values of the penetrating electrode including the through-hole having the large area of the opening and the penetrating electrode including the through-hole having the small area of the opening among the three kinds of the penetrating electrodes to determine states of connection of the penetrating electrodes.

摘要翻译： 提供一种可以容易地检查半导体衬底中的穿透电极的连接状态的半导体装置。 一种半导体装置的制造方法，其特征在于，在半导体基板上形成至少3种具有大面积，中间区域和小面积开口的通孔， 在具有不同开口面积的至少三种通孔的内表面上形成导电层，以形成穿透电极; 以及测量包括具有大面积开口的通孔的贯通电极和包括具有在三种穿透电极中具有小面积的开口的通孔的穿透电极的电阻值，以确定连接的状态 穿透电极。

公开(公告)号：US08786091B2

公开(公告)日：2014-07-22

申请号：US13059720

申请日：2009-10-19

申请人： Tadayoshi Muta

发明人： Tadayoshi Muta

IPC分类号： H01L23/532 ,  H01L21/60

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13144 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. In one embodiment a first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.

摘要翻译： 具有高纵横比的穿透电极的半导体装置通过低温处理制造。 在一个实施例中，分别设置在前表面侧和后表面侧的半导体衬底1的第一电极3和第二电极6通过填充在接触孔4中的导电体7和延伸部6a 第二电极6延伸到接触孔4.即使接触孔4具有高纵横比，也可以通过使用导电物体7来实现使用低温处理的成膜，而不是在底部形成第二电极6 接触孔4的一部分。

公开(公告)号：US08440565B2

公开(公告)日：2013-05-14

申请号：US12620660

申请日：2009-11-18

申请人： Tadayoshi Muta

发明人： Tadayoshi Muta

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/3025 ,  H01L2224/05552

摘要： There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning.

摘要翻译： 提供一种半导体装置的制造方法，其特征在于包括：在对应于电极焊盘的位置的点形成穿透半导体衬底的通孔; 在所述半导体衬底的后表面上形成绝缘膜，所述绝缘膜包括所述通孔的内部; 至少在所述通孔的开口部分中在所述绝缘膜的表面上从金属或无机绝缘体形成粘附确保层; 形成抗蚀剂层以在粘合确保层的底部蚀刻中用作掩模; 执行底部蚀刻以暴露电极焊盘; 去除抗蚀剂层以获得没有由底部蚀刻产生的表面不规则性的绝缘膜; 通过低温工艺形成阻挡层，种子层和导电层; 并进行图案化。

公开(公告)号：US07125810B2

公开(公告)日：2006-10-24

申请号：US10964714

申请日：2004-10-15

申请人： Tadayoshi Muta ,  Jin Tachikawa ,  Riichi Saito ,  Tadanori Suto ,  Manabu Takayama ,  Hiroyuki Morimoto

发明人： Tadayoshi Muta ,  Jin Tachikawa ,  Riichi Saito ,  Tadanori Suto ,  Manabu Takayama ,  Hiroyuki Morimoto

IPC分类号： H01L21/31

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

摘要： The semiconductor device of the present invention comprises a substrate; at least one through hole formed through the substrate between front and back surfaces of the substrate; an electrical connection portion formed by a semiconductor process on at least one surface of the front and back surfaces of the substrate in a vicinity of an end opening of the through hole; an insulating layer formed of an organic material on an inside surface of the through hole; and an electroconductive layer formed on an inside surface of the insulating layer, wherein the electrical connection portion is electrically connected to the electroconductive layer to be electrically connected to a side of the other surface of the substrate.

公开(公告)号：US08546801B2

公开(公告)日：2013-10-01

申请号：US12922530

申请日：2009-03-17

申请人： Tadayoshi Muta

发明人： Tadayoshi Muta

IPC分类号： H01L23/58

CPC分类号： G01R31/2853 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2924/09701 ,  H01L2924/12044

摘要： Provided is a semiconductor apparatus which may check a state of connection of a penetrating electrode in a semiconductor substrate with ease. A semiconductor apparatus manufacturing method includes: forming in a semiconductor substrate at least three kinds of the through-holes each having a large area, a middle area, and a small area of openings; forming a conductive layer on an inner surface of the at least three kinds of the through-holes having different areas of the openings to form the penetrating electrodes; and measuring resistance values of the penetrating electrode including the through-hole having the large area of the opening and the penetrating electrode including the through-hole having the small area of the opening among the three kinds of the penetrating electrodes to determine states of connection of the penetrating electrodes.

摘要翻译： 提供一种可以容易地检查半导体衬底中的穿透电极的连接状态的半导体装置。 一种半导体装置的制造方法，其特征在于，在半导体基板上形成至少3种具有大面积，中间区域和小面积开口的通孔， 在具有不同开口面积的至少三种通孔的内表面上形成导电层，以形成穿透电极; 以及测量包括具有大面积开口的通孔的贯通电极和包括具有在三种穿透电极中具有小面积的开口的通孔的穿透电极的电阻值，以确定连接的状态 穿透电极。

公开(公告)号：US20100127403A1

公开(公告)日：2010-05-27

申请号：US12620660

申请日：2009-11-18

申请人： Tadayoshi Muta

发明人： Tadayoshi Muta

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/49827 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/3025 ,  H01L2224/05552

摘要： There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning.

摘要翻译： 提供一种半导体装置的制造方法，其特征在于包括：在对应于电极焊盘的位置的点形成穿透半导体衬底的通孔; 在所述半导体衬底的后表面上形成绝缘膜，所述绝缘膜包括所述通孔的内部; 至少在所述通孔的开口部分中在所述绝缘膜的表面上从金属或无机绝缘体形成粘附确保层; 形成抗蚀剂层以在粘合确保层的底部蚀刻中用作掩模; 执行底部蚀刻以暴露电极焊盘; 去除抗蚀剂层以获得没有由底部蚀刻产生的表面不规则性的绝缘膜; 通过低温工艺形成阻挡层，种子层和导电层; 并进行图案化。

公开(公告)号：US06856023B2

公开(公告)日：2005-02-15

申请号：US10347937

申请日：2003-01-22

申请人： Tadayoshi Muta ,  Jin Tachikawa ,  Riichi Saito ,  Tadanori Suto ,  Manabu Takayama ,  Hiroyuki Morimoto

发明人： Tadayoshi Muta ,  Jin Tachikawa ,  Riichi Saito ,  Tadanori Suto ,  Manabu Takayama ,  Hiroyuki Morimoto

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

摘要： The semiconductor device of the present invention comprises a substrate; at least one through hole formed through the substrate between front and back surfaces of the substrate; an electrical connection portion formed by a semiconductor process on at least one surface of the front and back surfaces of the substrate in a vicinity of an end opening of the through hole; an insulating layer formed of an organic material on an inside surface of the through hole; and an electroconductive layer formed on an inside surface of the insulating layer, wherein the electrical connection portion is electrically connected to the electroconductive layer to be electrically connected to a side of the other surface of the substrate.