公开(公告)号：US5548249A

公开(公告)日：1996-08-20

申请号：US443577

申请日：1995-05-17

申请人： Masaya Sumita ,  Toshinori Maeda ,  Toru Kakiage

发明人： Masaya Sumita ,  Toshinori Maeda ,  Toru Kakiage

IPC分类号： H03L7/14 ,  H03L7/183 ,  H03L7/08 ,  H03L7/16

CPC分类号： H03L7/14 ,  H03L7/183

摘要： The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control circuit outputs two signals to the phase comparator as the first signal and the second signal, the phase difference between the two signals being substantially zero, and the voltage fixing control circuit fixing the voltage of the phase difference signal to a predetermined voltage at which the voltage control oscillator does not oscillate.

摘要翻译： 本发明的时钟发生器包括：输入切断控制电路，用于接收基准时钟和参考时钟，并响应复位信号输出第一信号和第二信号;相位比较器，用于输出指示相位的相位差信号 第一信号和第二信号之间的差; 电压控制振荡器，用于输出与所述相位差信号相对应的频率可变时钟; 以及电压固定控制电路，用于响应于所述复位信号来控制所述相位差信号的电压，其中，当所述复位信号处于第一电平时，所述输入关断控制电路将所述基准时钟输出到所述相位比较器 第一信号并将参考时钟作为第二信号输出到相位比较器，并且电压固定控制电路保持相位差信号的电压，并且当复位信号处于与第一电平不同的第二电平时，输入关断 控制电路将作为第一信号和第二信号的两个信号输出到相位比较器，两个信号之间的相位差基本为零，并且电压固定控制电路将相位差信号的电压固定为预定电压， 电压控制振荡器不振荡。

公开(公告)号：US07906800B2

公开(公告)日：2011-03-15

申请号：US12429758

申请日：2009-04-24

申请人： Masaya Sumita

发明人： Masaya Sumita

IPC分类号： H01L27/118

CPC分类号： H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.

摘要翻译： 半导体集成电路具有第一衬底电位赋予第一极性的第一衬底，具有与第一衬底电位不同的第二衬底电位的第一极性的第二衬底和第二衬底的第二衬底 极性与第一极性不同。 第一衬底与形成在衬底上的MOSFET的源极连接的电源或接地绝缘。 第三基板相对于第一和第二基板相邻地设置在第一和第二基板之间。 电路元件形成在第三基板上。

公开(公告)号：US07861202B2

公开(公告)日：2010-12-28

申请号：US11798985

申请日：2007-05-18

申请人： Masaya Sumita

发明人： Masaya Sumita

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F2217/78

摘要： Logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit between flip-flops are defined is input. The logic circuit information is analyzed to detect a logic circuit sandwiched by two flip-flops. The number of logic stages of the detected logic circuit is counted. It is determined, according to the counted number of logic stages, to which substrate potential a cell used for the logic circuit is to be connected.

摘要翻译： 输入经过设计的半导体集成电路的触发器和触发器之间的逻辑电路的逻辑电路信息。 分析逻辑电路信息以检测夹在两个触发器之间的逻辑电路。 对所检测的逻辑电路的逻辑级数进行计数。 根据计数的逻辑级数确定要连接用于逻辑电路的单元的哪个衬底电位。

公开(公告)号：US07639062B2

公开(公告)日：2009-12-29

申请号：US11949363

申请日：2007-12-03

申请人： Masaya Sumita

发明人： Masaya Sumita

IPC分类号： H03K17/0412

CPC分类号： H03K17/6872 ,  H03K17/04123 ,  H03K2217/0036

摘要： In an electronic device according to the present invention, a source of the first signal-wire drive transistor is connected to a first power supply, a drain of the first signal-wire drive transistor is connected to a signal wire, and a control circuit controls a gate voltage so that a current flowing in the signal wire is amplified toward a voltage to which a potential of the signal wire transits during the potential transition in the signal wire and further controls the gate voltage so that a voltage value obtained after the potential transition in the signal wire is retained after the potential transition in the signal wire.

摘要翻译： 在根据本发明的电子设备中，第一信号线驱动晶体管的源极连接到第一电源，第一信号线驱动晶体管的漏极连接到信号线，并且控制电路控制 栅极电压，使得在信号线中流动的电流被放大到信号线的电位在信号线的电位转变期间转移的电压，并进一步控制栅极电压，使得在电位转换之后获得的电压值 信号线中的信号线在电位转换后保持。

公开(公告)号：US07541841B2

公开(公告)日：2009-06-02

申请号：US11792777

申请日：2006-10-17

申请人： Masaya Sumita

发明人： Masaya Sumita

IPC分类号： H03K19/096

CPC分类号： H03K3/35625

摘要： In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D0 to D2 is selected using selection signals S0 to S2, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor Tr6 of the second dynamic circuit 1B is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected. This circuit is used in a predetermined circuit, such as, for example, a forwarding path of a data path, a crossbar bus switch, or an input portion of a reconfigurable processing unit.

摘要翻译： 在具有数据选择功能的动态触发电路中，例如，当使用选择信号S0选择了具有H值的数据时，第一节点N1为L，第二动态电路1B的第二节点N2为H ，使得输出信号Q具有H电平。 在这种情况下，当使用选择信号S0〜S2选择了多条数据D0〜D2时，第一节点N1为H，第二节点N2的电荷被放电，输出信号Q错误地 有一个L级。 然而，在这种情况下，输出节点N3为H，第四节点N4为L，第二动态电路1B的n型晶体管Tr6截止，从而防止第二节点N2放电。 因此，即使在没有选择任何数据的情况下，也能够确保令人满意的高速运转的正常运转。 该电路用于预定电路，例如数据路径的转发路径，交叉开关总线开关或可重构处理单元的输入部分。

公开(公告)号：US07541651B2

公开(公告)日：2009-06-02

申请号：US11497514

申请日：2006-08-02

申请人： Masaya Sumita

发明人： Masaya Sumita

IPC分类号： H01L23/50

CPC分类号： H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.

摘要翻译： 半导体集成电路具有第一衬底电位赋予第一极性的第一衬底，具有与第一衬底电位不同的第二衬底电位的第一极性的第二衬底和第二衬底的第二衬底 极性与第一极性不同。 第一衬底与形成在衬底上的MOSFET的源极连接的电源或接地绝缘。 第三基板相对于第一和第二基板相邻地设置在第一和第二基板之间。 电路元件形成在第三基板上。

公开(公告)号：US20090129138A1

公开(公告)日：2009-05-21

申请号：US12252563

申请日：2008-10-16

申请人： Masaya Sumita

发明人： Masaya Sumita

IPC分类号： G11C5/14 ,  G11C5/06 ,  H01L23/50 ,  H01L27/088 ,  H01L29/78

CPC分类号： G06F12/0893 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/1054 ,  G11C2207/2245

摘要： It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

摘要翻译： 本发明的目的是提供一种具有减少线路长度以实现更快处理的芯片布局的半导体集成电路。 缓存包括TAG存储器模块和高速缓存数据存储器模块。 高速缓存数据存储器模块被分为设置在TAG存储器模块两侧的第一和第二高速缓存数据存储器模块，数据TLB的输入/输出电路与TAG存储器模块的输入/输出电路相对， 跨总线区域的第一和第二高速缓存数据存储器模块的输入/输出电路，以减少线路长度以实现更快的处理。

公开(公告)号：US07498865B2

公开(公告)日：2009-03-03

申请号：US10511165

申请日：2004-02-19

申请人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Masaya Sumita

发明人： Shiro Sakiyama ,  Masayoshi Kinoshita ,  Masaya Sumita

IPC分类号： H03K3/01

CPC分类号： G05F1/565 ,  H03K19/00384

摘要： In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.

摘要翻译： 在本发明的半导体集成电路中，主电路2包括源极和基板彼此分离的MOS晶体管。 基板电位控制电路1控制主电路2的MOS晶体管的基板电位，使得主电路2的MOS晶体管的实际饱和电流值等于工作电源电压下的目标饱和电流值Ids Vdd。因此，即使半导体集成电路的工作电源电压降低，也可以抑制操作速度的变化。

公开(公告)号：US20080297204A1

公开(公告)日：2008-12-04

申请号：US12186934

申请日：2008-08-06

申请人： Masaya Sumita

发明人： Masaya Sumita

IPC分类号： H03K5/153

CPC分类号： H03K3/356139

摘要： In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H level. In this case, when none of a plurality of pieces of data is selected using a selection signal, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor of the second dynamic circuit is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

摘要翻译： 在具有数据选择功能的动态触发电路中，例如，当使用选择信号选择具有H值的数据时，第一节点N1为L，第二动态电路的第二节点N2为H， 输出信号具有H电平。 在这种情况下，当使用选择信号不选择多条数据时，第一节点N1为H，从而第二节点N2的电荷被放电，并且输出信号错误地具有L电平。 然而，在这种情况下，输出节点N3为H，第四节点N4为L，使得第二动态电路的n型晶体管截止，从而防止第二节点N2放电。 因此，即使在没有选择任何数据的情况下，也能够确保令人满意的高速运转的正常运转。

公开(公告)号：US07388411B2

公开(公告)日：2008-06-17

申请号：US11797951

申请日：2007-05-09

申请人： Yuta Araki ,  Isao Tanaka ,  Masaya Sumita

发明人： Yuta Araki ,  Isao Tanaka ,  Masaya Sumita

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03K19/0013

摘要： A semiconductor integrated circuit device according to the present invention includes: a sample circuit in which through current to be monitored flows during switching between transistors; a non-overlap circuit for outputting an output signal for the switching in the sample circuit; a current detector for detecting the through current flowing during the switching; and a current comparator in which a reference current value with respect to the through current has been set and which compares a current value detected by the current detector with the reference current value and outputs a result of the comparison to the non-overlap circuit.

摘要翻译： 根据本发明的半导体集成电路器件包括：采样电路，其中在晶体管之间切换期间待监视的通流电流流过; 用于输出用于在采样电路中切换的输出信号的非重叠电路; 电流检测器，用于检测在切换期间流过的通流; 以及电流比较器，其中已经设置了相对于直流电流的参考电流值，并且将电流检测器检测的电流值与参考电流值进行比较，并将比较结果输出到非重叠电路。