公开(公告)号：US07265989B2

公开(公告)日：2007-09-04

申请号：US10551845

申请日：2004-04-07

申请人： Masayoshi Son ,  Satoru Yoshikawa

发明人： Masayoshi Son ,  Satoru Yoshikawa

IPC分类号： H05K9/00

CPC分类号： H05K5/0269 ,  Y10S439/945 ,  Y10S439/946

摘要： A PC card is provided which can be used to add multiple capabilities to an information processing apparatus in cooperation with a conventional card only by the use of a single card slot.The PC card 1 comprises a card main body 10 which is provided with a connection plug 11 for connecting with the information processing apparatus 20 and a card connector 12 through which an additional card 30 can be connected, and which is connected to the information processing apparatus 20 to add multiple capabilities to the information processing apparatus; a pair of parallel rail members 13 serving to guide the additional card 30 for insertion; and a bridge member 14 connected between said pair of parallel rail members in order not to block the insertion path.

摘要翻译： 提供了一种PC卡，其可以仅通过使用单个卡槽才能与常规卡协同地向信息处理设备添加多个能力。 PC卡1包括卡主体10，其具有用于与信息处理装置20连接的连接插头11和可以连接附加卡30的卡连接器12，并且连接到信息处理装置 以向信息处理设备添加多个能力; 用于引导附加卡30插入的一对平行轨道构件13; 以及连接在所述一对平行导轨构件之间以便不阻挡插入路径的桥构件14。

公开(公告)号：US20060289619A1

公开(公告)日：2006-12-28

申请号：US10551845

申请日：2004-04-07

申请人： Masayoshi Son ,  Satoru Yoshikawa

发明人： Masayoshi Son ,  Satoru Yoshikawa

IPC分类号： G06F17/00

CPC分类号： H05K5/0269 ,  Y10S439/945 ,  Y10S439/946

摘要： A PC card is provided which can be used to add multiple capabilities to an information processing apparatus in cooperation with a conventional card only by the use of a single card slot. The PC card 1 comprises a card main body 10 which is provided with a connection plug 11 for connecting with the information processing apparatus 20 and a card connector 12 through which an additional card 30 can be connected, and which is connected to the information processing apparatus 20 to add multiple capabilities to the information processing apparatus; a pair of parallel rail members 13 serving to guide the additional card 30 for insertion; and a bridge member 14 connected between said pair of parallel rail members in order not to block the insertion path.

摘要翻译： 提供了一种PC卡，其可以仅通过使用单个卡槽才能与常规卡协同地向信息处理设备添加多个能力。 PC卡1包括卡主体10，其具有用于与信息处理设备20连接的连接插头11和可以连接附加卡30的卡连接器12，并且连接到信息处理设备 以向信息处理设备添加多个能力; 用于引导附加卡30插入的一对平行轨道构件13; 以及连接在所述一对平行导轨构件之间以便不阻挡插入路径的桥构件14。

公开(公告)号：US20070101035A1

公开(公告)日：2007-05-03

申请号：US10554398

申请日：2004-04-21

申请人： Masayoshi Son ,  Satoru Yoshikawa

发明人： Masayoshi Son ,  Satoru Yoshikawa

IPC分类号： H05K7/10 ,  G06F13/00

CPC分类号： G06F1/1632

摘要： A PC card and a method of controlling the PC card are provided which can be used to add multiple capabilities to an information processing apparatus in cooperation with a conventional card only by the use of a single card slot. The PC card 1 is provided with a multifunctional adapter unit 2 which controls data exchange between the information processing apparatus 20 and the function of the PC card or data exchange between the information processing apparatus 20 and the function of the PHS card, and a PC card function control unit 3 which controls the function of the PC card. The multifunctional adapter unit 2 is provided with a communication control unit 2a, an area builder unit 2b, an address control unit 2c, an interrupt request control unit 2d, and an interrupt cause register set 2e. A global card information structure and a global register area are built in the multifunctional adapter unit 2 by the area builder unit 2b in order to control the address operations to the PC card 1 by the information processing apparatus when the information processing apparatus refers to the PC card, and thereby both the memory spaces of the PC card function control unit 3 and the PHS card function control unit 4 can be accessed.

摘要翻译： 提供了一种PC卡和一种控制PC卡的方法，其可以仅通过使用单个卡槽才能与常规卡协同地向信息处理设备添加多个能力。 PC卡1设置有多功能适配器单元2，其控制信息处理设备20与PC卡的功能或信息处理设备20与PHS卡的功能之间的数据交换，以及PC卡 功能控制单元3，其控制PC卡的功能。 多功能适配器单元2设置有通信控制单元2a，区域构建器单元2b，地址控制单元2c，中断请求控制单元2d以及中断引起寄存器组2e。 为了在信息处理装置参考信息处理装置参考的情况下，由信息处理装置控制对PC卡1的地址操作，全域卡信息结构和全局寄存器区域由区域构建器单元2b构建在多功能适配器单元2中 PC卡，从而可以访问PC卡功能控制单元3和PHS卡功能控制单元4的两个存储空间。

公开(公告)号：US20070101036A1

公开(公告)日：2007-05-03

申请号：US10554401

申请日：2004-04-21

申请人： Masayoshi Son ,  Satoru Yoshikawa

发明人： Masayoshi Son ,  Satoru Yoshikawa

IPC分类号： H05K7/10 ,  G06F13/00

CPC分类号： G06F1/1632

摘要： A PC card and a method of controlling the PC card is provided which can be used to add multiple capabilities to an information processing apparatus in cooperation with a conventional card only by the use of a single card slot. The PC card 1 is provided with a multifunctional adapter unit 2 which controls data exchange between the information processing apparatus 20 and the function of the PC card or data exchange between the information processing apparatus 20 and the function of the PHS card, and a PC card function control unit 3 which controls the function of the PC card. The multifunctional adapter unit 2 of the PC card 1 is provided with a communication control unit 2a, an address control unit 2b, a driving system setting unit 2c, and an interrupt request control unit 2d. The address control unit 2b controls address operations in order that the address area used by the PC card function control unit 3 shall not overlap the address area used by the PHS card function control unit 4 in the memory space which is accessed by the information processing apparatus 20 through the PC card 1.

摘要翻译： 提供了一种PC卡和一种控制PC卡的方法，其可以仅通过使用单个卡槽而与常规卡一起用于向信息处理设备添加多个能力。 PC卡1设置有多功能适配器单元2，其控制信息处理设备20与PC卡的功能或信息处理设备20与PHS卡的功能之间的数据交换，以及PC卡 功能控制单元3，其控制PC卡的功能。 PC卡1的多功能适配器单元2设置有通信控制单元2a，地址控制单元2b，驱动系统设置单元2c和中断请求控制单元2d。 地址控制单元bb控制地址操作，以便由PC卡功能控制单元3使用的地址区域不与PHS卡功能控制单元4在由信息处理访问的存储器空间中使用的地址区域重叠 装置20通过PC卡1。

公开(公告)号：US07484025B2

公开(公告)日：2009-01-27

申请号：US10554401

申请日：2004-04-21

申请人： Masayoshi Son ,  Satoru Yoshikawa

发明人： Masayoshi Son ,  Satoru Yoshikawa

IPC分类号： G06F13/00

CPC分类号： G06F1/1632

摘要： A PC card and a method of controlling the PC card is provided which can be used to add multiple capabilities to an information processing apparatus in cooperation with a conventional card only by the use of a single card slot.The PC card 1 is provided with a multifunctional adapter unit 2 which controls data exchange between the information processing apparatus 20 and the function of the PC card or data exchange between the information processing apparatus 20 and the function of the PHS card, and a PC card function control unit 3 which controls the function of the PC card. The multifunctional adapter unit 2 of the PC card 1 is provided with a communication control unit 2a, an address control unit 2b, a driving system setting unit 2c, and an interrupt request control unit 2d. The address control unit 2b controls address operations in order that the address area used by the PC card function control unit 3 shall not overlap the address area used by the PHS card function control unit 4 in the memory space which is accessed by the information processing apparatus 20 through the PC card 1.

摘要翻译： 提供了一种PC卡和一种控制PC卡的方法，其可以仅通过使用单个卡槽而与常规卡一起用于向信息处理设备添加多个能力。 PC卡1设置有多功能适配器单元2，其控制信息处理设备20与PC卡的功能或信息处理设备20与PHS卡的功能之间的数据交换，以及PC卡 功能控制单元3，其控制PC卡的功能。 PC卡1的多功能适配器单元2设置有通信控制单元2a，地址控制单元2b，驱动系统设置单元2c和中断请求控制单元2d。 地址控制单元2b控制地址操作，以便由PC卡功能控制单元3使用的地址区域不与PHS卡功能控制单元4在由信息处理设备访问的存储器空间中使用的地址区域重叠 20通过PC卡1。

公开(公告)号：US06304998B1

公开(公告)日：2001-10-16

申请号：US09040321

申请日：1998-03-18

申请人： Yasuo Kamiya ,  Satoru Yoshikawa

发明人： Yasuo Kamiya ,  Satoru Yoshikawa

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method conducts logic simulation in an integrated circuit device, in which a macro containing logic circuits formed therein is included in a chip including a plurality of cells. The method determines a first delay parameter relating to an input terminal of an internal cell of the macro connected to the input terminal of the macro, and a second delay parameter relating to an output terminal of an internal cell of the macro connected to the output terminal of the macro. The method then determines delay time data for a whole logic circuit including the plurality of cells and the macro, in accordance with delay parameters determined for the macro, in which the first delay parameter is taken as an input terminal delay parameter and the second delay parameter is taken as an output terminal delay parameter; delay parameters determined for the plurality of cells; and connection data for the whole logic circuit. The method merges the determined delay time data for the whole logic circuit and internal delay time data for the macro so as to conduct a logic simulation for the whole logic circuit in accordance with the merged delay time data.

摘要翻译： 一种方法在集成电路器件中进行逻辑仿真，其中包含其中形成的逻辑电路的宏被包括在包括多个单元的芯片中。 该方法确定与连接到宏的输入端的宏的内部单元的输入端相关的第一延迟参数，以及与连接到输出端的宏的内部单元的输出端有关的第二延迟参数 的宏。 然后，该方法根据为宏确定的延迟参数确定包括多个小区和宏的整个逻辑电路的延迟时间数据，其中将第一延迟参数作为输入终端延迟参数，而第二延迟参数 作为输出端延迟参数; 对于所述多个单元确定的延迟参数; 和整个逻辑电路的连接数据。 该方法将确定的整个逻辑电路的延迟时间数据和宏的内部延迟时间数据合并，以便根据合并的延迟时间数据对整个逻辑电路进行逻辑仿真。

公开(公告)号：US5826907A

公开(公告)日：1998-10-27

申请号：US802519

申请日：1997-02-20

申请人： Kenichi Saito ,  Tetsuo Maki ,  Satoru Yoshikawa ,  Satoru Ichikawa

发明人： Kenichi Saito ,  Tetsuo Maki ,  Satoru Yoshikawa ,  Satoru Ichikawa

IPC分类号： B60R13/02 ,  B60R21/04 ,  B60R21/055 ,  B60R22/20 ,  B60R22/00

CPC分类号： B60R22/201 ,  B60R13/0206 ,  B60R13/025 ,  B60R21/04 ,  B60R21/055 ,  B60R2013/0287 ,  B60R2021/0435

摘要： A novel vehicle energy absorbing structure is disclosed, in which a hard member has a portion facing the compartment, a cover having a substantially U-shaped section is provided to cover the compartment side of the hard member, and an energy absorbing member is interposed between the cover and the hard member to absorb energy by plastic deformation. At the time of deformation of the cover caused under a pressure load not less than a predetermined value, at least a trigger portion formed in the cover provides a momentum for plastic deformation of the energy absorbing member. Thus a compact vehicle energy absorbing structure is provided which can absorb a sufficient amount of load.

摘要翻译： 公开了一种新颖的车辆能量吸收结构，其中硬质构件具有面向隔室的部分，提供具有大致U形截面的盖以覆盖硬构件的隔室侧，并且能量吸收构件介于 盖子和硬件通过塑性变形来吸收能量。 在不低于预定值的压力负载下引起的盖变形时，形成在盖中的至少一个触发部提供能量吸收构件的塑性变形的动量。 因此，提供了能够吸收足够量的负载的紧凑型车辆能量吸收结构。

公开(公告)号：US07219320B2

公开(公告)日：2007-05-15

申请号：US10807286

申请日：2004-03-24

申请人： Tetsuo Kawano ,  Satoru Yoshikawa ,  Toshikatsu Hosono ,  Shigenori Ichinose ,  Takashi Yoneda

发明人： Tetsuo Kawano ,  Satoru Yoshikawa ,  Toshikatsu Hosono ,  Shigenori Ichinose ,  Takashi Yoneda

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

摘要翻译： 根据栅极级的数量，在系数运算单元中计算作为分析对象的路径中的OCV系数，通过根据目标路径中的门级的数量消除每个门的延迟的变化，以及定时分析 通过使用考虑了门级数的OCV系数在定时分析单元中执行目标路径的变化，从而根据目标路径中的门级数减少整个路径的变化程度，从而使 考虑到半导体集成电路的芯片的变化，可以进行准确的时序分析。

公开(公告)号：US20060135613A1

公开(公告)日：2006-06-22

申请号：US10517646

申请日：2003-06-12

申请人： Makoto Shimazaki ,  Osamu Sakurai ,  Kanako Hirai ,  Klaus Urbahns ,  Noriyuki Yamamoto ,  Satoru Yoshikawa ,  Masaomi Umeda ,  Masaomi Tajimi

发明人： Makoto Shimazaki ,  Osamu Sakurai ,  Kanako Hirai ,  Klaus Urbahns ,  Noriyuki Yamamoto ,  Satoru Yoshikawa ,  Masaomi Umeda ,  Masaomi Tajimi

IPC分类号： A61K31/198 ,  A61K31/195 ,  C07C237/38

CPC分类号： C07C235/34

摘要： The present invention relates to carboxamides which are useful as an active ingredient of pharmaceutical preparations. The carboxamides of the present invention have IP receptor antagonistic activity, and can be used for the prophylaxis and treatment of diseases associated with IP receptor antagonistic activity. Such diseases include urological diseases or disorder as follows: bladder outlet obstruction, overactive bladder, urinary incontinence, detrusor hyper-reflexia, detrusor instability, reduced bladder capacity, frequency of micturition, urge incontinence, stress incontinence, bladder hyperreactivity, benighn prostatic hypertrophy (BPH), prostatitis, urinary frequency, nocturia, urinary urgency, pelvic hypersensitivity, urethritis, pelvic pain syndrome, prostatodynia, cystitis, or idiophatic bladder hypersensitivity. The compounds of the present invention are also useful for treatment of pain including, but not limited to inflammatory pain, neuropathic pain, acute pain, chronic pain, dental pain, premenstrual pain, visceral pain, headaches, and the like; hypotension; hemophilia and hemorrhage; and inflammation, since the diseases are alleviated by treatment with an IP receptor antagonist.

摘要翻译： 本发明涉及可用作药物制剂活性成分的羧酰胺。 本发明的甲酰胺具有IP受体拮抗活性，可用于预防和治疗与IP受体拮抗活性相关的疾病。 这些疾病包括泌尿系统疾病或紊乱，如下：膀胱出口阻塞，膀胱过度活动，尿失禁，逼尿肌反射反射，逼尿肌不稳定，膀胱容量减少，排尿频率，急迫性尿失禁，压力性尿失禁，膀胱反应过度，前列腺肥大 ），前列腺炎，尿频，夜尿症，尿急，盆腔超敏反应，尿道炎，盆腔疼痛综合征，前列腺痛，膀胱炎或自发性膀胱过敏。 本发明的化合物还可用于治疗疼痛，包括但不限于炎性疼痛，神经性疼痛，急性疼痛，慢性疼痛，牙痛，经前痛，内脏痛，头痛等; 低血压 血友病和出血; 和炎症，因为通过用IP受体拮抗剂治疗来减轻疾病。

公开(公告)号：US06012833A

公开(公告)日：2000-01-11

申请号：US878080

申请日：1997-06-18

申请人： Satoru Yoshikawa

发明人： Satoru Yoshikawa

IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82 ,  H01L27/02 ,  G06F19/00

CPC分类号： H01L27/0207 ,  G06F17/5022

摘要： A method of manufacturing an integration circuit device that includes generating logic library data with respect to a macro that includes a predetermined macro core and boundary cells positioned near input and output terminals of the macro. The logic library data includes delay characteristic data of the boundary cells given as attribute data to the input and output terminals. A logic circuit, that includes a plurality of cells and the macro, is designed, with the cells being connected to the macro core through the boundary cells connected to the input and output terminals. A delay time of the macro is calculated based on the delay characteristic data with respect to the designed logic circuit. A logic simulation on the designed logic circuit is effected based on the calculated delay time.

摘要翻译： 一种制造积分电路器件的方法，包括相对于包含预定宏核心的微距产生逻辑库数据，以及位于该宏的输入和输出端附近的边界单元。 逻辑库数据包括作为输入和输出端子的属性数据给出的边界单元的延迟特性数据。 设计包括多个单元和宏的逻辑电路，其中单元通过连接到输入和输出端子的边界单元连接到宏核。 基于相对于设计的逻辑电路的延迟特性数据来计算宏的延迟时间。 基于所计算的延迟时间，对设计的逻辑电路进行逻辑仿真。