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1.发明授权Encoding apparatus for encoding binary signals generated from binarized multivalued syntax elements and method for performing the same 有权用于编码由二值化多值语法元素生成的二进制信号的编码装置及其执行方法公开(公告)号：US08406308B2
公开(公告)日：2013-03-26
申请号：US12761493
申请日：2010-04-16
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： An encoding device encoding binary signals using arithmetic-encoding. The encoding device includes a binarization unit binarizing multivalued syntax elements in order to generate the binary signals. The generated binary signals are stored on an intermediate buffer. Further, the encoding device includes an arithmetic-encoding unit performing the arithmetic-encoding on the binary signals stored on the intermediate buffer. Additionally, the generated binary signals are binary representations of values of the multivalued syntax elements.
摘要翻译： 使用算术编码对二进制信号进行编码的编码装置。 编码装置包括二值化单元，二值化多值语法元素以便生成二进制信号。 生成的二进制信号存储在中间缓冲器上。 此外，编码装置包括对存储在中间缓冲器上的二进制信号执行算术编码的算术编码单元。 另外，生成的二进制信号是多值语法元素的值的二进制表示。
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2.发明授权Decoding-processing apparatus for decoding bitstreams encoded in accordance with an arithmetic-encoding system in image compression and method for performing the same 有权用于对图像压缩中的算术编码系统进行编码的比特流进行解码的解码处理装置及其执行方法公开(公告)号：US08081683B2
公开(公告)日：2011-12-20
申请号：US12761507
申请日：2010-04-16
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译： 一种使用中间格式解码比特流的解码处理装置。 该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元 （4）根据概率解码输入比特流，由此提供解码数据。 该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从 存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值， 检测单元（7）。
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公开(公告)号：US20100232516A1
公开(公告)日：2010-09-16
申请号：US12761507
申请日：2010-04-16
IPC分类号： H04N7/26
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译： 一种使用中间格式解码比特流的解码处理装置。 该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元 （4）根据概率解码输入比特流，由此提供解码数据。 该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从 存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值， 检测单元（7）。
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公开(公告)号：US20100232496A1
公开(公告)日：2010-09-16
申请号：US12761493
申请日：2010-04-16
IPC分类号： H04N7/26
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
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公开(公告)号：US07724830B2
公开(公告)日：2010-05-25
申请号：US11665063
申请日：2005-11-02
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译： 一种使用中间格式解码比特流的解码处理装置。 该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元 （4）根据概率解码输入比特流，由此提供解码数据。 该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从 存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值， 检测单元（7）。
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公开(公告)号：US20090225865A1
公开(公告)日：2009-09-10
申请号：US11665063
申请日：2005-11-02
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus (1) comprising: a context-calculating unit (2) operable to calculate the probability of symbols contained in incoming bitstreams; a parameter-generating unit (3) operable to generate parameters for use in the context-calculating unit (2); an arithmetic decoding-calculating unit (4) operable to decode the incoming bitstreams in accordance with the probability, thereby providing decoded data; a stream-converting unit (5) operable to convert the decoded data into intermediate bitstreams; a storage unit (6) operable to store the intermediate bitstreams; a synchronization-detecting unit (7) operable to detect calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing; and a multivalued calculating unit (8) operable to permit the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译： 一种解码处理装置（1），包括：上下文计算单元（2），用于计算输入比特流中包含的符号的概率; 参数产生单元（3），用于产生在所述上下文计算单元（2）中使用的参数; 算术解码计算单元，用于根据概率解码输入比特流，从而提供解码数据; 流转换单元（5），用于将解码数据转换成中间比特流; 存储单元（6），用于存储中间比特流; 同步检测单元，用于从存储单元（6）馈送的中间比特流检测计算开始定时，从而提供检测到的计算开始时刻; 以及多值计算单元（8），其可操作以允许从所述同步检测单元（7）与所检测到的计算开始定时同步地将从所述存储单元（6）馈送的中间比特流多值化。
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7.发明授权Image encoding device, image decoding device, and integrated circuit used therein 有权图像编码装置，图像解码装置及其中使用的集成电路公开(公告)号：US08179972B2
公开(公告)日：2012-05-15
申请号：US11628733
申请日：2005-06-07
申请人： Hidekatsu Ozeki , Masayasu Iguchi , Takahiro Nishi , Hiroaki Toida , Hiroto Tomita , Akihiko Inoue , Takashi Hashimoto
发明人： Hidekatsu Ozeki , Masayasu Iguchi , Takahiro Nishi , Hiroaki Toida , Hiroto Tomita , Akihiko Inoue , Takashi Hashimoto
IPC分类号： H04N7/12
CPC分类号： H04N19/42 , H04N19/122 , H04N19/60
摘要： An image decoding device and an encoding device include an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing.
摘要翻译： 图像解码装置和编码装置包括用于进行运算处理的算术单元，运算单元存储运算结果的算术数据存储单元，选择是否读入要输入的像素数据的输入选择单元 从压缩图像数据或从存储在算术数据存储单元中的像素数据获得的运算单元，以及将读取的像素数据输入到运算单元，以及运算控制单元，用于根据所使用的变换模式和算术运算数， 算术单元，读取由输入选择单元输入到运算单元的像素数据的目的地以及由算术单元进行算术处理的像素数据的组合和乘法系数， 算术处理。
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8.发明申请Image Encoding Device, Image Decoding Device, and Integrated Circuit Used Therein 有权图像编码装置，图像解码装置及其中使用的集成电路公开(公告)号：US20080049832A1
公开(公告)日：2008-02-28
申请号：US11628733
申请日：2005-06-07
申请人： Hidekatsu Ozeki , Masayasu Iguchi , Takahiro Nishi , Hiroaki Toida , Hiroto Tomita , Akihiko Inoue , Takashi Hashimoto
发明人： Hidekatsu Ozeki , Masayasu Iguchi , Takahiro Nishi , Hiroaki Toida , Hiroto Tomita , Akihiko Inoue , Takashi Hashimoto
IPC分类号： H04B1/66
CPC分类号： H04N19/42 , H04N19/122 , H04N19/60
摘要： An image decoding device and an image encoding device according to the present invention includes an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing, the arithmetic control unit previously defining an arithmetic procedure in each transform mode for each unit executable in one arithmetic operation in the arithmetic unit in association with the number of arithmetic operations.
摘要翻译： 根据本发明的图像解码装置和图像编码装置包括：运算单元，用于进行运算处理;算术数据存储单元，用于存储运算单元的算术结果;输入选择单元，用于选择是否读取像素数据， 从压缩图像数据或从存储在算术数据存储单元中的像素数据输入到运算单元，并将读取的像素数据输入到运算单元，以及运算控制单元，用于基于所使用的变换模式和 算术单元中的算术运算的数量，由输入选择单元输入到运算单元的像素数据的目的地以及由运算单元计算的运算处理对象的像素数据的组合 算术单元和乘法器系数，运算控制单元先前定义算术 在算术单元中的一个算术运算中，每个单元的每个变换模式的过程与算术运算的数量相关联。
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公开(公告)号：US20070183508A1
公开(公告)日：2007-08-09
申请号：US10591177
申请日：2005-08-02
申请人： Shintaro Kudo , Takahiro Nishi , Masayasu Iguchi
发明人： Shintaro Kudo , Takahiro Nishi , Masayasu Iguchi
CPC分类号： H04N19/86 , H04N19/117 , H04N19/134 , H04N19/174 , H04N19/176 , H04N19/186 , H04N19/61 , H04N19/82
摘要： Provided is an image decoding device which can eliminate block distortion and also can restrain decrease of a processing speed, even if an order of decoding blocks is changed. Such an image decoding device (100) has: a variable length decoding unit (111) or the like which sequentially decodes the blocks; a frame memory (102); a de-blocking filtering unit (119) which applies filtering processing to each decoded block; switches (103and 104) in the first executing status, which stores the block into the frame memory (102) every time the block is decoded, and applies the filtering processing to the stored blocks; switches (103 and 104) in the second executing status, which applies the filtering processing to the block to be applied with the filtering processing every time the block is decoded; and a control unit (101) which switches between the first executing status and the second executing status of the switches (103 and 104).
摘要翻译： 提供了一种能够消除块失真的图像解码装置，并且即使改变解码块的顺序，也可以抑制处理速度的降低。 这种图像解码装置（100）具有：对块进行顺序解码的可变长度解码部（111）等; 帧存储器（102）; 对每个解码块应用滤波处理的解块滤波单元（119）; 开关（103和104）处于第一执行状态，每当该块解码时将该块存储到帧存储器（102）中，并将该过滤处理应用于存储的块; 在第二执行状态下的开关（103和104），每当该块被解码时，将过滤处理应用于要被应用于滤波处理的块; 以及在开关（103和104）的第一执行状态和第二执行状态之间切换的控制单元（101）。
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公开(公告)号：US20070254697A1
公开(公告)日：2007-11-01
申请号：US11661919
申请日：2005-09-05
申请人： Toshiyasu Sugio , Satoshi Kondo , Masayasu Iguchi , Takahiro Nishi , Tadamasa Toma , Hisao Sasai
发明人： Toshiyasu Sugio , Satoshi Kondo , Masayasu Iguchi , Takahiro Nishi , Tadamasa Toma , Hisao Sasai
IPC分类号： H04M1/00
CPC分类号： H04M11/04 , H04M1/66 , H04M1/72538
摘要： The present invention is a mobile terminal device comprising a data transmission/reception unit (103) for transmitting and receiving data, a memory unit (104) or a memory card unit (105) for storing data, a main power supply (109), a secondary power supply (110), an emergency data transmission unit (112) for transmitting data to a predetermined server, terminal, or external device, and an emergency mode control unit (102) for, when the data transmission/reception unit (103) receives data for setting an emergency mode, setting the power supply so as not to be turned off, and controlling the emergency data transmission unit (112) so as to save the data stored in the memory unit (104) or the memory card unit (105) into the predetermined server, terminal, or external device. According to the mobile terminal device of the present invention, when there occurs loss, or theft, or accident that might lose important data, protection of the important data and prevention of unauthorized use can be reliably carried out.
摘要翻译： 本发明是一种移动终端装置，包括用于发送和接收数据的数据发送/接收单元（103），用于存储数据的存储单元（104）或存储卡单元（105），主电源（109） 二次电源（110），用于向预定服务器，终端或外部设备发送数据的紧急数据发送单元（112），以及用于当数据发送/接收单元（103） ）接收用于设置紧急模式的数据，将电源设置为不被关闭，并且控制紧急数据传输单元（112）以便存储存储在存储单元（104）或存储卡单元 （105）进入预定的服务器，终端或外部设备。 根据本发明的移动终端装置，当发生丢失，盗窃或可能丢失重要数据的事故时，可以可靠地执行重要数据的保护和防止未经授权的使用。
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