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    Capacitor element with an opening portion formed in a peripheral circuit
    1.
    发明授权
    Capacitor element with an opening portion formed in a peripheral circuit 有权
    具有形成在外围电路中的开口部分的电容器元件

    公开(公告)号：US06921960B2

    公开(公告)日：2005-07-26

    申请号：US09984718

    申请日：2001-10-31

    申请人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae ,  Atsuhiro Sato ,  Yuji Takeuchi

    发明人： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae ,  Atsuhiro Sato ,  Yuji Takeuchi

    IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/08 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00

    CPC分类号： H01L27/11526 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/11531

    摘要： A semiconductor device includes a structure in which a first electrode layer, an inter-electrode insulating film and a second electrode layer are laminated in a main circuit in this order, and includes a capacitor element having a lower electrode formed of the same layer as the first electrode layer, a charge storage layer formed of the same layer as the inter-electrode insulating film, and an upper electrode formed of the second electrode layer. The semiconductor device further includes an opening portion formed in the charge storage layer, the opening portion having a bottom to which the lower electrode is exposed, and a first region electrically connected to the lower electrode via the opening portion and electrically isolated from the upper electrode, the first region being formed of the same layer as the second electrode layer.

    摘要翻译： 半导体器件包括其中第一电极层，电极间绝缘膜和第二电极层依次层叠在主电路中的结构，并且包括电容器元件，其具有由与第一电极层相同的层形成的下电极 第一电极层，由与电极间绝缘膜相同的层形成的电荷存储层和由第二电极层形成的上电极。 半导体装置还包括形成在电荷存储层中的开口部分，开口部分具有露出下部电极的底部，以及经由开口部分电连接到下部电极并与上部电极电隔离的第一区域 所述第一区域由与所述第二电极层相同的层形成。

    Non-volatile semiconductor memory device with multi-layer gate structure
    2.
    发明授权
    Non-volatile semiconductor memory device with multi-layer gate structure 失效
    具有多层栅极结构的非易失性半导体存储器件

    公开(公告)号：US06853029B2

    公开(公告)日：2005-02-08

    申请号：US10155086

    申请日：2002-05-28

    申请人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

    发明人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

    摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

    摘要翻译： 半导体器件包括半导体衬底，源极和漏极区，沟道区，栅极绝缘膜，电荷存储层和控制栅电极。 源区和漏区包括第一导电类型的第一杂质。 沟道区域包括第二导电类型的第二杂质。 栅极绝缘膜包括位于沟道区域的至少一部分正上方的区域中的第二杂质。 电荷存储层形成在栅极绝缘膜上。 控制栅电极设置在电荷存储层上。 控制栅电极形成在电荷存储层上，并且通过设置在电荷存储层的一部分上的连接部分电连接到电荷存储层，所述连接部位于栅极绝缘区域的至少一部分的正上方 膜包括第二杂质。

    Method of manufacturing an electrically erasable programmable read-only memory (EEPROM)
    6.
    发明授权
    Method of manufacturing an electrically erasable programmable read-only memory (EEPROM) 有权
    制造电可擦除可编程只读存储器（EEPROM）的方法

    公开(公告)号：US07504294B2

    公开(公告)日：2009-03-17

    申请号：US10881180

    申请日：2004-07-01

    申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

    摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

    摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

    Semiconductor device with a selection gate and a peripheral gate
    7.
    发明授权
    Semiconductor device with a selection gate and a peripheral gate 有权
    具有选择栅极和外围栅极的半导体器件

    公开(公告)号：US07417281B2

    公开(公告)日：2008-08-26

    申请号：US11733488

    申请日：2007-04-10

    申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    IPC分类号： H01L29/94

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

    摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

    摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
    半导体器件和制造方法

    公开(公告)号：US20070187749A1

    公开(公告)日：2007-08-16

    申请号：US11733488

    申请日：2007-04-10

    申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

    摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

    摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

    Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
    9.
    发明授权
    Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same 失效
    具有存储单元部分和外围电路部分的半导体存储器件及其制造方法

    公开(公告)号：US07442985B2

    公开(公告)日：2008-10-28

    申请号：US11283742

    申请日：2005-11-22

    申请人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

    发明人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11541 ,  H01L27/11543

    摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

    摘要翻译： 在半导体存储器件的外围电路部分中形成用于分离半导体层的元件区域的元件隔离区域，并且第一导电层形成有元件区域，其间插入有第一绝缘膜。 第二导电层形成在第一导电层上以延伸到元件隔离区域中。 位于元件隔离区域内的第二导电层的该部分的表面被暴露，并且在第二导电层上形成第三导电层，其间插入有第二绝缘膜。 此外，触点电连接到第二导电层的暴露表面。