公开(公告)号：US20130241068A1

公开(公告)日：2013-09-19

申请号：US13597337

申请日：2012-08-29

申请人： Masayuki TANAKA ,  Kenichiro Toratani ,  Kazuhiro Matsuo

发明人： Masayuki TANAKA ,  Kenichiro Toratani ,  Kazuhiro Matsuo

IPC分类号： H01L21/02 ,  H01L23/498

CPC分类号： H01L21/02697 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： According to one embodiment, a method for forming a semiconductor device includes: forming a first underlayer film that contains a first atom selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals; forming, on the first underlayer film, a second underlayer film that contains a second atom selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals, the second atom being an atom not contained in the first underlayer film; and forming, on the second underlayer film, a silicon oxide film by a CVD or ALD method by use of a silicon source containing at least one of an ethoxy group, a halogen group, an alkyl group, and an amino group, or a silicon source of a siloxane system.

摘要翻译： 根据一个实施例，一种形成半导体器件的方法包括：形成含有选自锗，铝，钨，铪，钛，钽，镍，钴和碱土金属中的第一原子的第一下层膜; 在第一下层膜上形成含有选自锗，铝，钨，铪，钛，钽，镍，钴和碱土金属的第二原子的第二下层膜，第二原子不是原子 包含在第一下层膜中; 以及通过使用含有乙氧基，卤素基团，烷基和氨基中的至少一个的硅源或通过CVD或ALD方法在硅的第二下层膜上形成氧化硅膜的硅或硅 硅氧烷体系的来源。

公开(公告)号：US20090189213A1

公开(公告)日：2009-07-30

申请号：US12354200

申请日：2009-01-15

申请人： Kazuhiro MATSUO ,  Masayuki TANAKA ,  Atsuhiro SUZUKI

发明人： Kazuhiro MATSUO ,  Masayuki TANAKA ,  Atsuhiro SUZUKI

IPC分类号： H01L29/792 ,  H01L21/283 ,  H01L21/764

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/94

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 Å.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底，具有由以形成在衬底的表面中的预定间隔分开形成的多个沟槽分开形成的多个有源区;形成在衬底的上表面上的第一栅极绝缘膜， 区域，通过依次沉积形成在栅极绝缘膜的上表面上的电荷存储层，第二栅极绝缘膜和控制栅极绝缘膜而形成的存储单元晶体管的栅电极，每个区域中埋设的元件隔离绝缘膜 沟槽，并且由涂覆型氧化物膜形成，并且在半导体衬底和元件隔离绝缘膜之间的边界上形成在每个沟槽内的绝缘膜，所述绝缘膜包含非转移金属原子并且具有不大于5的膜厚度。

公开(公告)号：US20120094476A1

公开(公告)日：2012-04-19

申请号：US13051031

申请日：2011-03-18

申请人： Masayuki TANAKA ,  Kazuhiro Matsuo ,  Yoshio Ozawa

发明人： Masayuki TANAKA ,  Kazuhiro Matsuo ,  Yoshio Ozawa

IPC分类号： H01L21/28

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L27/11582

摘要： According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.

摘要翻译： 根据一个实施例，提供一种制造半导体器件的方法，包括通过氮化作为主要成分的含有硅的半导体区域的下面的区域的表面和以硅和氧为主要的绝缘区域来形成氮化物膜 并且与半导体区域相邻，相对于氮化物膜进行氧化，将形成在绝缘区域上的氮化物膜的一部分转换为氧化膜，并且使形成在该半导体层上的氮化膜的一部分 半导体区域作为电荷存储绝缘膜的至少一部分，在电荷存储绝缘膜上形成块绝缘膜，并在块绝缘膜上形成栅极电极膜。

公开(公告)号：US20130240978A1

公开(公告)日：2013-09-19

申请号：US13601372

申请日：2012-08-31

申请人： Masayuki TANAKA ,  Kazuhiro Matsuo

发明人： Masayuki TANAKA ,  Kazuhiro Matsuo

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L27/11521

摘要： According to one embodiment, a nonvolatile semiconductor memory device has a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control electrode formed on the second insulating film. In the nonvolatile semiconductor memory device, the second insulating film has a laminated structure that has a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film, a first atom is provided at an interface between the first silicon oxide film and the first silicon nitride film, and/or at an interface between the second silicon oxide film and the first silicon nitride film, and the first atom is selected from the group consisting of aluminum, boron, and alkaline earth metals.

摘要翻译： 根据一个实施例，非易失性半导体存储器件具有半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及控制 电极形成在第二绝缘膜上。 在非易失性半导体存储器件中，第二绝缘膜具有层叠结构，该叠层结构具有第一氧化硅膜，第一氮化硅膜和第二氧化硅膜，第一原子设置在第一氧化硅膜 和/或在第二氧化硅膜和第一氮化硅膜之间的界面处，并且第一原子选自铝，硼和碱土金属。

公开(公告)号：US20130069142A1

公开(公告)日：2013-03-21

申请号：US13423633

申请日：2012-03-19

申请人： Kazuhiro MATSUO ,  Masayuki TANAKA ,  Hirofumi IIKAWA

发明人： Kazuhiro MATSUO ,  Masayuki TANAKA ,  Hirofumi IIKAWA

IPC分类号： H01L29/792 ,  H01L21/762

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/76232 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor device includes an element isolation region having an element isolation insulating film therein; an active region delineated by the element isolation region; agate insulating film formed in the active region; a charge storage layer above the gate insulating film; and an interelectrode insulating film. The interelectrode insulating film is formed in a first region above an upper surface of the element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a stack of a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a second silicon nitride film. A control electrode layer is formed above the interelectrode insulating film. The second silicon oxide film is thinner in the first region than in the third region.

摘要翻译： 半导体器件包括其中具有元件隔离绝缘膜的元件隔离区域; 由元件隔离区域划定的活动区域; 形成在活性区域中的玛瑙绝缘膜; 栅极绝缘膜上方的电荷存储层; 和电极间绝缘膜。 电极间绝缘膜形成在元件隔离绝缘膜的上表面上方的第一区域，沿着电荷存储层的侧壁的第二区域和电荷存储层的上表面上方的第三区域。 电极间绝缘膜包括第一氧化硅膜，第一氮化硅膜，第二氧化硅膜和第二氮化硅膜的堆叠。 在电极间绝缘膜的上方形成控制电极层。 第二氧化硅膜在第一区域比在第三区域薄。

公开(公告)号：US20120193699A1

公开(公告)日：2012-08-02

申请号：US13353512

申请日：2012-01-19

申请人： Masayuki TANAKA

发明人： Masayuki TANAKA

IPC分类号： H01L29/792 ,  H01L21/762

CPC分类号： H01L29/788 ,  H01L27/11517 ,  H01L29/42336 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7881

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate; an element isolation insulating film buried in the semiconductor substrate so as to isolate adjacent element; a memory cell having a first insulating film and a charge accumulation film; a second insulating film formed on the charge accumulation films of the memory cells and the element isolation insulating film; and a control electrode film formed on the second insulating film. An upper surface of the element isolation insulating film is lower than an upper surface of the charge accumulation film, the second insulating film is provided with a cell upper portion on the charge accumulation film and an inter-cell portion on the element isolation insulating film, and a dielectric constant of the cell upper portion is lower than a dielectric constant of the inter-cell portion.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体衬底; 埋置在半导体衬底中以隔离相邻元件的元件隔离绝缘膜; 具有第一绝缘膜和电荷累积膜的存储单元; 形成在存储单元的电荷累积膜和元件隔离绝缘膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极膜。 元件隔离绝缘膜的上表面低于电荷累积膜的上表面，第二绝缘膜在电荷累积膜上设置有单元上部，在元件隔离绝缘膜上设置单元间部分， 并且单元上部的介电常数低于单元间部分的介电常数。

公开(公告)号：US20110154159A1

公开(公告)日：2011-06-23

申请号：US12970651

申请日：2010-12-16

申请人： Masayuki TANAKA

发明人： Masayuki TANAKA

IPC分类号： G06F11/08 ,  H03M13/09

CPC分类号： H03M13/091

摘要： A cyclic redundancy check code generating circuit successively receives one or more parallel data as input, and repetitively performs a prescribed operation for calculating a cyclic redundancy check code for each parallel data, based on the parallel data and on an initial value or an earlier calculated cyclic redundancy check code. The cyclic redundancy check code generating circuit includes: a plurality of sub-operation units which, based on the initial value and the parallel data, perform sub-operations in different pipeline stages, respectively, by dividing the prescribed operation in a bit length direction of the parallel data; and a correction unit which, based on the initial value and the earlier calculated cyclic redundancy check code, corrects the cyclic redundancy check code calculated by the sub-operation units.

摘要翻译： 循环冗余校验码产生电路连续地接收一个或多个并行数据作为输入，并且重复执行用于针对每个并行数据计算循环冗余校验码的规定操作，基于并行数据和初始值或较早计算的循环 冗余校验码。 循环冗余校验码产生电路包括：多个子操作单元，其基于初始值和并行数据，分别通过将规定的操作除以位长度方向 并行数据; 以及校正单元，其基于初始值和较早计算的循环冗余校验码来校正由子操作单元计算的循环冗余校验码。

公开(公告)号：US20100049489A1

公开(公告)日：2010-02-25

申请号：US12544595

申请日：2009-08-20

申请人： Masayuki TANAKA

发明人： Masayuki TANAKA

IPC分类号： G06G7/57

CPC分类号： G06F17/5018 ,  G06F2217/16

摘要： A system for a flow simulation using Moving Particle Semi-implicit method, includes a processor representing a target incompressible fluid by a plurality of particles grouped according to different particle sizes depending on a spatial resolution required at positions in a simulation domain; temporarily updating a velocity and a position coordinate of each particle to a first velocity and a first position coordinate by implicitly calculating a variation of the velocity of each particle due to a viscosity of the incompressible fluid in each of a plurality of time steps having a predetermined time interval; and updating the first velocity and the first position coordinate to a second velocity and a second position coordinate of each particle at a next time step of each time step by calculating a velocity correction of the first velocity due to a pressure gradient of the incompressible fluid using the first velocity.

摘要翻译： 一种使用运动粒子半隐式方法进行流动模拟的系统，包括根据模拟域中的位置所需的空间分辨率，根据不同的粒度分组的多个粒子代表目标不可压缩流体的处理器; 通过在具有预定的多个时间步长的每个时间步骤中隐含地计算由于不可压缩流体的粘度引起的每个粒子的速度的变化，将每个粒子的速度和位置坐标临时更新为第一速度和第一位置坐标 时间间隔; 以及通过计算由于所述不可压缩流体的压力梯度而导致的第一速度的速度校正，使用在每个时间步长的下一个时间步长，将所述第一速度和所述第一位置坐标更新为每个粒子的第二速度和第二位置坐标 第一速度。

公开(公告)号：US20120034772A1

公开(公告)日：2012-02-09

申请号：US13274030

申请日：2011-10-14

申请人： Hirokazu ISHIDA ,  Masayuki TANAKA ,  Yoshio OZAWA

发明人： Hirokazu ISHIDA ,  Masayuki TANAKA ,  Yoshio OZAWA

IPC分类号： H01L21/28

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/513

摘要： A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof and is so formed that the upper surface thereof will be set with height between those of the upper and bottom surfaces of the first conductor. The second insulator includes a three-layered insulating film formed of a silicon oxide film, a silicon oxynitride film and a silicon oxide film formed on the first conductor and element isolation insulator. The second conductor is formed on the second insulator.

摘要翻译： 非易失性半导体存储器件包括第一绝缘体，第一导体，元件隔离绝缘体，第二绝缘体和第二导体。 第一绝缘体形成在基板的主表面上，第一导体形成在第一绝缘体上。 元件隔离绝缘体在其栅极宽度方向上填充到第一绝缘体的两个侧表面的至少一部分中，并且第一导体的栅极宽度方向的两个侧表面被形成为使得其上表面将被设置 其高度在第一导体的上表面和底表面之间。 第二绝缘体包括由形成在第一导体和元件隔离绝缘体上的氧化硅膜，氧氮化硅膜和氧化硅膜形成的三层绝缘膜。 第二导体形成在第二绝缘体上。

公开(公告)号：US20130240976A1

公开(公告)日：2013-09-19

申请号：US13601266

申请日：2012-08-31

申请人： Masayuki TANAKA

发明人： Masayuki TANAKA

IPC分类号： H01L21/02 ,  H01L29/792

CPC分类号： H01L21/02329 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/792

摘要： In accordance with an embodiment, a nonvolatile semiconductor memory device includes a substrate including a semiconductor layer including an active region, a first insulating film on the active region, a charge storage layer on the first insulating film, an element isolation insulating film defining the active region, a second insulating film, and a control electrode on the second insulating film. The top surface of the element isolation insulating film is placed at a height between the top surface and the bottom surface of the charge storage layer, thereby forming a step constituted of the charge storage layer and the element isolation insulating film. The second insulating film covers the step and the charge storage layer. The second insulating film includes a first silicon oxide film and a first silicon nitride film on the first silicon oxide film. Nitrogen concentration in the first silicon nitride film is non-uniform.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件包括：衬底，该衬底包括具有有源区的半导体层，有源区上的第一绝缘膜，第一绝缘膜上的电荷存储层，限定有源区的元件隔离绝缘膜 区域，第二绝缘膜和第二绝缘膜上的控制电极。 元件隔离绝缘膜的上表面被放置在电荷存储层的顶表面和底表面之间的高度处，从而形成由电荷存储层和元件隔离绝缘膜构成的步骤。 第二绝缘膜覆盖步骤和电荷存储层。 第二绝缘膜包括在第一氧化硅膜上的第一氧化硅膜和第一氮化硅膜。 第一氮化硅膜中的氮浓度不均匀。