Method and system for determining an element conversion characteristic contemporaneous with converting and input signal in a signal converter
    1.
    发明授权
    Method and system for determining an element conversion characteristic contemporaneous with converting and input signal in a signal converter 有权
    用于确定与信号转换器中的转换和输入信号同时的元件转换特性的方法和系统

    公开(公告)号:US06411232B1

    公开(公告)日:2002-06-25

    申请号:US09409779

    申请日:1999-09-30

    IPC分类号: H03M110

    CPC分类号: H03M3/386 H03M3/388 H03M3/424

    摘要: A converter continuously converts an input signal (110) to an output signal (112) even during correction and compensation. A primary converter (124) converts the signal along a forward primary path (104). A feedback converter (140) along a feedback path (106) outputs a feedback signal (116). A reference device (136) employs reference indicator (134) to provide a digital reference signal (135). A selection device (132) passes the digital reference signal (135) to an element (204) of the feedback converter (140) for outputting reference portion (208) of the feedback signal (116). The passing of the digital reference signal (135) to the element (204) is contemporaneous with the converting of the input signal (110) to the output signal (112). The evaluator (142) determines a conversion characteristic of the element (204) by employing a characteristic of the reference indicator (134).

    摘要翻译: 即使在校正和补偿期间,A转换器也将输入信号(110)连续地转换为输出信号(112)。 主转换器(124)沿着前向主路径(104)转换信号。 沿反馈路径(106)的反馈转换器(140)输出反馈信号(116)。 参考装置(136)使用参考指示器(134)来提供数字参考信号(135)。 选择装置(132)将数字参考信号(135)传递到反馈转换器(140)的元件(204),用于输出反馈信号(116)的参考部分(208)。 将数字参考信号(135)传递到元件(204)同时与输入信号(110)转换为输出信号(112)。 评估器(142)通过采用参考指示符(134)的特性来确定元件(204)的转换特性。

    Using Virtual Table Protections to Prevent the Exploitation of Object Corruption Vulnerabilities
    2.
    发明申请
    Using Virtual Table Protections to Prevent the Exploitation of Object Corruption Vulnerabilities 有权
    使用虚拟表格保护来防止对象损坏漏洞利用

    公开(公告)号:US20120144480A1

    公开(公告)日:2012-06-07

    申请号:US12958668

    申请日:2010-12-02

    IPC分类号: G06F21/00

    CPC分类号: G06F21/6218 G06F2221/2143

    摘要: The subject disclosure is directed towards preventing the exploitation by malicious code of object state corruption vulnerabilities, such as use-after-free vulnerabilities. An object class is configured with a secret cookie in a virtual function table of the object, e.g., inserted at compile time. An instrumentation check inserted in the program code evaluates the secret cookie to determine whether the object state has been corrupted before object access (e.g., a call to one of the object's methods) is allowed. If corrupted, access to the object is prevented by the instrumentation check. Another instrumentation check may be used to determine whether the object's virtual table pointer points to a location outside of the module that contains the legitimate virtual function table; if so, object access is prevented.

    摘要翻译: 该主题披露旨在防止恶意代码利用对象状态破坏漏洞(例如使用后免费漏洞)。 对象类在对象的虚拟功能表中配置有秘密cookie,例如在编译时插入。 插入程序代码中的检测检查将评估秘密cookie,以确定对象状态是否在对象访问之前已被破坏(例如,对对象的方法之一的调用)。 如果损坏,仪器检查会阻止对对象的访问。 可以使用另一种仪器检查来确定对象的虚拟表指针是否指向包含合法虚拟功能表的模块之外的位置; 如果是这样,则可以防止对象访问。

    DIGITAL PULSE WIDTH MODULATION FOR HALF BRIDGE AMPLIFIERS
    3.
    发明申请
    DIGITAL PULSE WIDTH MODULATION FOR HALF BRIDGE AMPLIFIERS 有权
    用于半桥式放大器的数字脉冲宽度调制

    公开(公告)号:US20100109767A1

    公开(公告)日:2010-05-06

    申请号:US12262127

    申请日:2008-10-30

    IPC分类号: H03F3/38 H03F3/217

    CPC分类号: H03F3/217

    摘要: A switching amplifier drives a load or audio transducer. A digital integral noise shaping circuit converts a digital input such as audio content to an output digital pulse width modulated signal using an integrator. The integrator integrates the digital input, a variable frequency reference pulse width modulated signal and an inverse of the output digital pulse width modulated signal. A half bridge amplifier receives the output digital pulse width modulated signal and drives the load or audio transducer. A variable frequency generator generates the variable frequency reference pulse width modulated signal with an approximately equal duty ratio or alternatively varies the variable frequency pulse width modulated signal above and below about a fifty percent duty ratio.

    摘要翻译: 开关放大器驱动负载或音频传感器。 数字积分噪声整形电路使用积分器将诸如音频内容的数字输入转换为输出数字脉宽调制信号。 积分器将数字输入,可变频率参考脉冲宽度调制信号和输出数字脉宽调制信号的反相相结合。 半桥放大器接收输出数字脉宽调制信号并驱动负载或音频传感器。 可变频率发生器以大致相等的占空比产生可变频率参考脉冲宽度调制信号,或者可选地改变高于和低于约百分之五十占空比的可变频率脉宽调制信号。

    Using virtual table protections to prevent the exploitation of object corruption vulnerabilities
    4.
    发明授权
    Using virtual table protections to prevent the exploitation of object corruption vulnerabilities 有权
    使用虚拟表保护来防止利用对象损坏的漏洞

    公开(公告)号:US08683583B2

    公开(公告)日:2014-03-25

    申请号:US12958668

    申请日:2010-12-02

    IPC分类号: G06F21/00

    CPC分类号: G06F21/6218 G06F2221/2143

    摘要: The subject disclosure is directed towards preventing the exploitation by malicious code of object state corruption vulnerabilities, such as use-after-free vulnerabilities. An object class is configured with a secret cookie in a virtual function table of the object, e.g., inserted at compile time. An instrumentation check inserted in the program code evaluates the secret cookie to determine whether the object state has been corrupted before object access (e.g., a call to one of the object's methods) is allowed. If corrupted, access to the object is prevented by the instrumentation check. Another instrumentation check may be used to determine whether the object's virtual table pointer points to a location outside of the module that contains the legitimate virtual function table; if so, object access is prevented.

    摘要翻译: 该主题披露旨在防止恶意代码利用对象状态破坏漏洞(例如使用后免费漏洞)。 对象类在对象的虚拟功能表中配置有秘密cookie,例如在编译时插入。 插入程序代码中的检测检查将评估秘密cookie,以确定对象状态是否在对象访问之前已被破坏(例如,对对象的方法之一的调用)。 如果损坏,仪器检查会阻止对对象的访问。 可以使用另一种仪器检查来确定对象的虚拟表指针是否指向包含合法虚拟功能表的模块之外的位置; 如果是这样,则可以防止对象访问。

    Variable gain low noise amplifier and method
    6.
    发明授权
    Variable gain low noise amplifier and method 有权
    可变增益低噪声放大器及方法

    公开(公告)号:US06930554B2

    公开(公告)日:2005-08-16

    申请号:US10623047

    申请日:2003-07-18

    摘要: A variable gain control amplifier (10) and method provides a substantially constant input impedance and output impedance, and provides a substantially constant noise figure and third order harmonic. The variable gain control amplifier (10) includes an amplifier stage including at least a first intermediate fixed gain stage (22) operative to produce a first intermediate signal (30) in response to the input signal (20). The variable gain control amplifier (10) further includes at least a second intermediate fixed gain stage (24) operative to produce an output signal (18) in response to the first intermediate signal (30). A feedback circuit (16) is operative to produce a gain control signal (32) in response to the output signal (18). A gain control circuit (26) is coupled to the at least first intermediate fixed gain stage (22) and the second intermediate fixed gain stage (24), and receives the gain control signal (32) to control an amplitude of the intermediate signal (30).

    摘要翻译: 可变增益控制放大器(10)和方法提供基本恒定的输入阻抗和输出阻抗,并且提供基本上恒定的噪声系数和三阶谐波。 可变增益控制放大器(10)包括放大器级,至少包括第一中间固定增益级(22),用于响应输入信号(20)产生第一中间信号(30)。 可变增益控制放大器(10)还包括至少第二中间固定增益级(24),其响应于第一中间信号(30)而产生输出信号(18)。 反馈电路(16)用于响应于输出信号(18)产生增益控制信号(32)。 增益控制电路(26)耦合到至少第一中间固定增益级(22)和第二中间固定增益级(24),并且接收增益控制信号(32)以控制中间信号 30)。

    Offset compensated differential amplifier
    7.
    发明授权
    Offset compensated differential amplifier 有权
    偏置补偿差分放大器

    公开(公告)号:US06750704B1

    公开(公告)日:2004-06-15

    申请号:US10340335

    申请日:2003-01-09

    IPC分类号: H03F102

    CPC分类号: H03F3/45753 H03F2200/331

    摘要: A differential amplifier comprises a differential input stage including first and second input devices and has first and second input electrodes and first and second output terminals. A differential load stage includes first and second load devices having first and second control electrodes respectively. The load stage is coupled to the differential input stage and to the first and second output terminals. First and second separate capacitive biasing networks are coupled to the first and second output terminals and respectively to the first and second control electrodes. During an offset-cancellation phase, the input electrodes are coupled to a common voltage. During an amplification phase, a differential input signal is applied to the input electrodes.

    摘要翻译: 差分放大器包括具有第一和第二输入装置的差分输入级,并具有第一和第二输入电极以及第一和第二输出端子。 差分负载级包括分别具有第一和第二控制电极的第一和第二负载装置。 负载级耦合到差分输入级以及第一和第二输出端。 第一和第二分离电容偏置网络耦合到第一和第二输出端子,并分别耦合到第一和第二控制电极。 在偏移消除阶段期间,输入电极耦合到公共电压。 在放大阶段期间,差分输入信号被施加到输入电极。

    Automatic threshold control for multi-level signals
    8.
    发明授权
    Automatic threshold control for multi-level signals 失效
    多级信号的自动阈值控制

    公开(公告)号:US5521941A

    公开(公告)日:1996-05-28

    申请号:US620601

    申请日:1990-11-29

    IPC分类号: H04L25/06

    摘要: Symbol recovery for multi-level digital signals has traditionally been difficult because of the nature of the eye pattern output by the discriminator (103), and especially its response to a noisy or impeded signal environment. This method and apparatus for recovery thresholds adjusts (411 and 417) to the current state of the discriminator (103) output of the received signal, based on an attenuated (301) version of that signal. Using a fast adjust mode and slow adjust mode, the threshold generating circuitry (331 and 361) adapts to the signal based on data from the received signal fed into lock detectors (329 and 359) which determine the mode to use.

    摘要翻译: 传统上由于鉴别器(103)输出的眼图的性质,特别是其对噪声或阻碍的信号环境的响应,多级数字信号的符号恢复是困难的。 该恢复阈值的方法和装置基于该信号的衰减(301)版本,调整(411和417)到接收信号的鉴别器(103)输出的当前状态。 使用快速调整模式和慢速调整模式,阈值产生电路(331和361)根据来自确定使用模式的锁定检测器(329和359)的接收信号的数据适应信号。

    Data transmission system receiver having phase-independent bandwidth
control
    10.
    发明授权
    Data transmission system receiver having phase-independent bandwidth control 失效
    具有相位独立带宽控制的数据传输系统接收器

    公开(公告)号:US5182761A

    公开(公告)日:1993-01-26

    申请号:US649083

    申请日:1991-01-31

    CPC分类号: H04L7/0331 H04L7/08 H04L7/10

    摘要: A data transmission system receiver is disclosed which receives a formatted data stream (302) and operates in one of at least a first bandwidth mode and a second bandwidth mode. The formatted data stream (302) comprises a plurality of data edges (108, 110) and is sampled by a first clock signal (320). A plurality of clock edges (102, 104) defining transitions from one logic state to another is used to define "early" and "late" data edge occurrences. These occurrences are accumulated in accumulators (310, 312) and used as inputs to a clock counter (318) which produces a phase-adjusted clock signal (320). Additionally, the data transmission receiver comprises a detector (330) for detecting when a limited data stream (306) is synchronized with the phase-adjusted clock signal (320) and, in accordance with a predetermined algorithm, is able to switch the phase-lock circuit from the first bandwidth mode to the second bandwidth mode.

    摘要翻译: 公开了一种数据传输系统接收机,其接收格式化的数据流(302)并且以至少第一带宽模式和第二带宽模式之一进行操作。 格式化数据流(302)包括多个数据边缘(108,110),并由第一时钟信号(320)进行采样。 使用定义从一个逻辑状态到另一逻辑状态的转换的多个时钟边缘(102,104)来定义“早期”和“晚期”数据边缘出现。 这些事件被累积在累加器(310,312)中,并用作产生相位调整时钟信号(320)的时钟计数器(318)的输入。 另外,数据传输接收机包括检测器(330),用于检测有限数据流(306)何时与相位调整时钟信号(320)同步,并且根据预定算法,能够切换相位调制信号 锁定电路从第一带宽模式到第二带宽模式。