摘要:
A converter continuously converts an input signal (110) to an output signal (112) even during correction and compensation. A primary converter (124) converts the signal along a forward primary path (104). A feedback converter (140) along a feedback path (106) outputs a feedback signal (116). A reference device (136) employs reference indicator (134) to provide a digital reference signal (135). A selection device (132) passes the digital reference signal (135) to an element (204) of the feedback converter (140) for outputting reference portion (208) of the feedback signal (116). The passing of the digital reference signal (135) to the element (204) is contemporaneous with the converting of the input signal (110) to the output signal (112). The evaluator (142) determines a conversion characteristic of the element (204) by employing a characteristic of the reference indicator (134).
摘要:
The subject disclosure is directed towards preventing the exploitation by malicious code of object state corruption vulnerabilities, such as use-after-free vulnerabilities. An object class is configured with a secret cookie in a virtual function table of the object, e.g., inserted at compile time. An instrumentation check inserted in the program code evaluates the secret cookie to determine whether the object state has been corrupted before object access (e.g., a call to one of the object's methods) is allowed. If corrupted, access to the object is prevented by the instrumentation check. Another instrumentation check may be used to determine whether the object's virtual table pointer points to a location outside of the module that contains the legitimate virtual function table; if so, object access is prevented.
摘要:
A switching amplifier drives a load or audio transducer. A digital integral noise shaping circuit converts a digital input such as audio content to an output digital pulse width modulated signal using an integrator. The integrator integrates the digital input, a variable frequency reference pulse width modulated signal and an inverse of the output digital pulse width modulated signal. A half bridge amplifier receives the output digital pulse width modulated signal and drives the load or audio transducer. A variable frequency generator generates the variable frequency reference pulse width modulated signal with an approximately equal duty ratio or alternatively varies the variable frequency pulse width modulated signal above and below about a fifty percent duty ratio.
摘要:
The subject disclosure is directed towards preventing the exploitation by malicious code of object state corruption vulnerabilities, such as use-after-free vulnerabilities. An object class is configured with a secret cookie in a virtual function table of the object, e.g., inserted at compile time. An instrumentation check inserted in the program code evaluates the secret cookie to determine whether the object state has been corrupted before object access (e.g., a call to one of the object's methods) is allowed. If corrupted, access to the object is prevented by the instrumentation check. Another instrumentation check may be used to determine whether the object's virtual table pointer points to a location outside of the module that contains the legitimate virtual function table; if so, object access is prevented.
摘要:
An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.
摘要:
A variable gain control amplifier (10) and method provides a substantially constant input impedance and output impedance, and provides a substantially constant noise figure and third order harmonic. The variable gain control amplifier (10) includes an amplifier stage including at least a first intermediate fixed gain stage (22) operative to produce a first intermediate signal (30) in response to the input signal (20). The variable gain control amplifier (10) further includes at least a second intermediate fixed gain stage (24) operative to produce an output signal (18) in response to the first intermediate signal (30). A feedback circuit (16) is operative to produce a gain control signal (32) in response to the output signal (18). A gain control circuit (26) is coupled to the at least first intermediate fixed gain stage (22) and the second intermediate fixed gain stage (24), and receives the gain control signal (32) to control an amplitude of the intermediate signal (30).
摘要:
A differential amplifier comprises a differential input stage including first and second input devices and has first and second input electrodes and first and second output terminals. A differential load stage includes first and second load devices having first and second control electrodes respectively. The load stage is coupled to the differential input stage and to the first and second output terminals. First and second separate capacitive biasing networks are coupled to the first and second output terminals and respectively to the first and second control electrodes. During an offset-cancellation phase, the input electrodes are coupled to a common voltage. During an amplification phase, a differential input signal is applied to the input electrodes.
摘要:
Symbol recovery for multi-level digital signals has traditionally been difficult because of the nature of the eye pattern output by the discriminator (103), and especially its response to a noisy or impeded signal environment. This method and apparatus for recovery thresholds adjusts (411 and 417) to the current state of the discriminator (103) output of the received signal, based on an attenuated (301) version of that signal. Using a fast adjust mode and slow adjust mode, the threshold generating circuitry (331 and 361) adapts to the signal based on data from the received signal fed into lock detectors (329 and 359) which determine the mode to use.
摘要:
In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.
摘要:
A data transmission system receiver is disclosed which receives a formatted data stream (302) and operates in one of at least a first bandwidth mode and a second bandwidth mode. The formatted data stream (302) comprises a plurality of data edges (108, 110) and is sampled by a first clock signal (320). A plurality of clock edges (102, 104) defining transitions from one logic state to another is used to define "early" and "late" data edge occurrences. These occurrences are accumulated in accumulators (310, 312) and used as inputs to a clock counter (318) which produces a phase-adjusted clock signal (320). Additionally, the data transmission receiver comprises a detector (330) for detecting when a limited data stream (306) is synchronized with the phase-adjusted clock signal (320) and, in accordance with a predetermined algorithm, is able to switch the phase-lock circuit from the first bandwidth mode to the second bandwidth mode.