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    Cobalt barrier for nickel silicidation of a gate electrode
    3.
    发明授权
    Cobalt barrier for nickel silicidation of a gate electrode 有权
    用于栅电极的镍硅化的钴屏障

    公开(公告)号：US06541866B1

    公开(公告)日：2003-04-01

    申请号：US09778113

    申请日：2001-02-07

    申请人： Jacques J. Bertrand ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  George J. Kluth

    发明人： Jacques J. Bertrand ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  George J. Kluth

    IPC分类号： H01L2348

    CPC分类号： H01L21/28052 ,  H01L29/4941

    摘要： Nickel silicidation of a gate electrode is controlled using a cobalt barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of cobalt thereon and an upper polycrystalline silicon layer on the cobalt layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel suicide and a cobalt silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.

    摘要翻译： 使用钴阻挡层控制栅电极的镍硅化。 实施例包括形成包括下多晶硅层，钴层上的钴层和钴层上的上多晶硅层的栅电极结构，沉积镍层和硅化物，由此将上多晶硅层转化为硅化镍， 形成防止镍与下部多晶硅层反应的硅化钴阻挡层。

    Fully nickel silicided metal gate with shallow junction formed
    4.
    发明授权
    Fully nickel silicided metal gate with shallow junction formed 有权
    全镍硅化金属栅极，形成浅结

    公开(公告)号：US06555453B1

    公开(公告)日：2003-04-29

    申请号：US10058219

    申请日：2002-01-29

    申请人： Qi Xiang ,  Christy Mei-Chu Woo ,  George J. Kluth

    发明人： Qi Xiang ,  Christy Mei-Chu Woo ,  George J. Kluth

    IPC分类号： H01L2128

    CPC分类号： H01L29/66507 ,  H01L21/2257 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/4975 ,  H01L29/6659

    摘要： Semiconductor devices having fully metal silicided gate electrodes, and methods for making the same, are disclosed. The devices have shallow S/D extensions with depths of less than about 500 Å. The methods for making the subject semiconductor devices employ diffusion of dopant from metal suicides to form shallow S/D extensions, followed by high energy implantation and activation, and metal silicidation to form S/D junctions having metal silicide connect regions and a fully metal silicided electrode.

    摘要翻译： 公开了具有完全金属硅化物栅电极的半导体器件及其制造方法。 这些器件具有深度小于约500的浅的S / D延伸。 制造本发明的半导体器件的方法是使用掺杂剂从金属硅化物扩散以形成浅的S / D扩展，接着是高能量注入和激活，以及金属硅化以形成具有金属硅化物连接区域和全金属硅化物的S / D结 电极。

    HDP treatment for reduced nickel silicide bridging
    5.
    发明授权
    HDP treatment for reduced nickel silicide bridging 有权
    HDP处理用于还原硅化镍桥接

    公开(公告)号：US06521529B1

    公开(公告)日：2003-02-18

    申请号：US09679880

    申请日：2000-10-05

    申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Ercan Adem ,  Robert A. Huertas

    发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Ercan Adem ,  Robert A. Huertas

    IPC分类号： H01L2144

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6656 ,  Y10S257/90

    摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented, after silicidation and removal of any unreacted nickel, by treating the exposed surfaces of the silicon nitride sidewall spacers with a HDP plasma to oxidize nickel silicide thereon forming a surface layer comprising silicoin oxide and silicon oxynitride. Embodiments include treating the silicon nitride sidewall spacers with a HDP plasma to form a surface silicon oxide/silicon oxynitride region having a thickness of about 40 Å to about 50 Å.

    摘要翻译： 通过用HDP等离子体处理氮化硅侧壁间隔物的暴露表面以氧化硅化镍，在硅化和除去任何未反应的镍之后，阻止栅电极上的硅化镍层与氮化硅侧壁间隔物的源/漏区之间的桥接 其上形成包含硅氧烷氧化物和氮氧化硅的表面层。 实施例包括用HDP等离子体处理氮化硅侧壁间隔物以形成厚度为大约至大约的表面氧化硅/氧氮化硅区域。

    Physical vapor deposition of nickel
    6.
    发明授权
    Physical vapor deposition of nickel 失效
    镍的物理气相沉积

    公开(公告)号：US06806172B1

    公开(公告)日：2004-10-19

    申请号：US09826078

    申请日：2001-04-05

    申请人： Christy Mei-Chu Woo ,  Eric N. Paton ,  Susan Tover

    发明人： Christy Mei-Chu Woo ,  Eric N. Paton ,  Susan Tover

    IPC分类号： H01L21425

    CPC分类号： H01L29/665 ,  H01L21/324 ,  H01L29/7833

    摘要： Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.

    摘要翻译： 通过在将镍沉积在基底上或在两个或更多个基底或两者的处理之间加热沉积室来实现镍膜形成。 实施例包括在具有暴露的硅表面的复合材料上形成硅化镍，通过将衬底引入具有至少一个用于加热室的加热元件的PVD室，并将镍层直接沉积在复合材料的暴露的硅表面上，同时加热 具有加热元件的室。

    Nitrogen-plasma treatment for reduced nickel silicide bridging
    7.
    发明授权
    Nitrogen-plasma treatment for reduced nickel silicide bridging 有权
    氮等离子体处理用于还原硅化镍桥接

    公开(公告)号：US06661067B1

    公开(公告)日：2003-12-09

    申请号：US10260514

    申请日：2002-10-01

    申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

    发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

    IPC分类号： H01L2994

    CPC分类号： H01L29/665 ,  H01L21/3115 ,  Y10S257/90

    摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

    摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

    Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode
    8.
    发明授权
    Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
    一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极

    公开(公告)号：US06861350B1

    公开(公告)日：2005-03-01

    申请号：US10464508

    申请日：2003-06-19

    申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

    发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H10L21/4763 ,  H10L21/44

    CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

    摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.

    摘要翻译： 微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。 实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中 的富硅钽硅氮化物。 在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。 实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

    METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED
    9.
    发明授权
    METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED 失效
    用于通过形成测试样本设备来确定阻隔层有效性的方法，并且使用用于制造生产半导体器件的金属渗透测量技术和形成的测试样本设备

    公开(公告)号：US06617176B1

    公开(公告)日：2003-09-09

    申请号：US10152861

    申请日：2002-05-21

    申请人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

    发明人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

    IPC分类号： H01L2166

    CPC分类号： H01L22/24 ,  G01N1/32 ,  H01L22/34

    摘要： A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

    摘要翻译： 通过形成测试样品并测量从金属化层（40）穿过阻挡层（30）（例如耐火材料）的铜（Cu）渗透性来确定沉积的薄共形阻挡层（30）的有效性的方法（M） 金属，其氮化物，它们的碳化物或其它化合物）通过薄的绝缘介电层（20）（例如SiO 2）和半导体（10）衬底（例如Si）中，其中迁移金属 离子和半导体离子被检测/监测，并且其中检测/监测包括（1）剥离绝缘介电层（20）和阻挡层（30）的至少一部分和（2）检查半导体衬底（10） ）表面，从而提高互连可靠性，提高耐迁移性，提高耐腐蚀性，减少铜扩散，从而形成试样装置。

    Nickel silicide process using UDOX to prevent silicide shorting
    10.
    发明授权
    Nickel silicide process using UDOX to prevent silicide shorting 有权
    使用UDOX的硅化镍工艺防止硅化物短路

    公开(公告)号：US06507123B1

    公开(公告)日：2003-01-14

    申请号：US09679878

    申请日：2000-10-05

    申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jacques J. Bertrand

    发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jacques J. Bertrand

    IPC分类号： H01L27088

    CPC分类号： H01L29/665 ,  H01L29/6656

    摘要： A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide. first and second sets of sidewall spacers and nickel suicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed undoped silicon oxide and are respectively disposed adjacent the first and second sidewalls. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The second set of sidewall spacers being formed from undoped silicon oxide prevents the formation of nickel silicide on the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.

    摘要翻译： MOSFET半导体器件包括衬底，栅电极，栅极氧化物。 第一和第二组侧壁间隔物和镍硅化物层。 栅极氧化物设置在栅极电极和衬底之间，并且衬底包括源极/漏极区域。 栅电极具有第一和第二相对的侧壁，并且第一组侧壁间隔物形成为未掺杂的氧化硅，并且分别设置在第一和第二侧壁附近。 第二组侧壁间隔件由氮化硅形成，并且分别设置在第一组侧壁间隔件附近。 硅化镍层设置在源/漏区和栅电极上。 由未掺杂的氧化硅形成的第二组侧壁间隔件防止在第二组侧壁间隔物上形成硅化镍。 还公开了制造半导体器件的方法。