公开(公告)号：US20220393704A1

公开(公告)日：2022-12-08

申请号：US17888475

申请日：2022-08-16

申请人： MEDIATEK INC.

发明人： Chieh-Hsun Hsiao ,  Ming-Chou Wu ,  Wen-Chang Lee ,  Narayanan Baskaran ,  Wei-Hsin Tseng ,  Jenwei Ko ,  Po-Sen Tseng ,  Hsin-Hung Chen ,  Chih-Yuan Lin ,  Caiyi Wang

IPC分类号： H04B1/00

摘要： A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

公开(公告)号：US11469781B2

公开(公告)日：2022-10-11

申请号：US16776513

申请日：2020-01-30

申请人： MEDIATEK INC.

发明人： Chieh-Hsun Hsiao ,  Ming-Chou Wu ,  Wen-Chang Lee ,  Narayanan Baskaran ,  Wei-Hsin Tseng ,  Jenwei Ko ,  Po-Sen Tseng ,  Hsin-Hung Chen ,  Chih-Yuan Lin ,  Caiyi Wang

IPC分类号： H04L5/22 ,  H04B1/00

摘要： A transmission interface between at least a master module and a slave module is proposed. The transmission interface includes a predetermined number of physical transmission medium(s). Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated, and the predetermined number is not smaller than a number of intermediate frequency (IF) stream(s) to be transmitted.

公开(公告)号：US20240211673A1

公开(公告)日：2024-06-27

申请号：US18522162

申请日：2023-11-28

申请人： Mediatek INC.

发明人： Pang-Yen Chin ,  Yu-Sian Lin ,  Ri-Cheng Zeng ,  Chi-Shun Cheng ,  Wei-Hsin Tseng ,  Kuan-Ta Chen ,  Chia-Hsin Hu

IPC分类号： G06F30/392 ,  H01L27/02

CPC分类号： G06F30/392 ,  H01L27/0207 ,  G06F2111/20

摘要： A method for designing an integrated circuit layout includes: generating an analog standard cell library and designing the integrated circuit layout by using at least the analog standard cell library, where the step of generating the analog standard cell library includes creating a target analog standard cell that is included in the analog standard cell library and does not violate layout rules of digital standard cells. Another method for designing an integrated circuit layout includes: generating a mixed-signal standard cell library and designing the integrated circuit layout by using at least the mixed-signal standard cell library, where the step of generating the mixed-signal standard cell library includes creating a target mixed-signal standard cell that is included in the mixed-signal standard cell library and does not violate layout rules of digital standard cells.

公开(公告)号：US20210021279A1

公开(公告)日：2021-01-21

申请号：US16894860

申请日：2020-06-07

申请人： MEDIATEK INC.

发明人： Wei-Hsin Tseng

IPC分类号： H03M1/74 ,  H03M3/00 ,  H03M1/06

摘要： A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.

公开(公告)号：US09722746B2

公开(公告)日：2017-08-01

申请号：US15165088

申请日：2016-05-26

申请人： MediaTek Inc.

发明人： Stacy Ho ,  Wei-Hsin Tseng

IPC分类号： H04L5/00 ,  H04B1/12 ,  H03M1/46 ,  H03M1/06 ,  H03M3/00 ,  H04B1/00 ,  H04L27/26

CPC分类号： H04L5/0041 ,  H03M1/0617 ,  H03M1/466 ,  H03M3/406 ,  H03M3/41 ,  H03M3/426 ,  H03M3/47 ,  H04B1/0075 ,  H04B1/123 ,  H04L5/001 ,  H04L27/2647

摘要： Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

公开(公告)号：US09154152B1

公开(公告)日：2015-10-06

申请号：US14576315

申请日：2014-12-19

申请人： MediaTek Inc.

发明人： Pao-Cheng Chiu ,  Wei-Hsin Tseng

IPC分类号： H03M1/06 ,  H03M1/46 ,  H03M1/08 ,  H03M1/20

CPC分类号： H03M1/468 ,  H03M1/0607 ,  H03M1/08 ,  H03M1/1061

摘要： Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k−1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k−1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.

摘要翻译： 提供模数转换器（ADC）。 ADC包含第一个电容数模转换器（CDAC）和一个控制电路。 包括n位的CDAC被配置为将n位的第k位连接到第一参考电压以提供第一模拟信号，使用第0到第（k-1）位将第一模拟信号转换为第一数字码， 比第k位更不重要，将n位的第k位连接到第二参考电压以提供第二模拟信号，并且使用第0到第（k-1）位将第二模拟信号转换为第二数字码， 不如第k位显着。 控制电路被配置为基于第一和第二数字码估计第k位的权重。

公开(公告)号：US11929767B2

公开(公告)日：2024-03-12

申请号：US17888475

申请日：2022-08-16

申请人： MEDIATEK INC.

发明人： Chieh-Hsun Hsiao ,  Ming-Chou Wu ,  Wen-Chang Lee ,  Narayanan Baskaran ,  Wei-Hsin Tseng ,  Jenwei Ko ,  Po-Sen Tseng ,  Hsin-Hung Chen ,  Chih-Yuan Lin ,  Caiyi Wang

IPC分类号： H04W52/52 ,  H04B1/00 ,  H04B17/345

CPC分类号： H04B1/0057

摘要： A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

公开(公告)号：US10958284B2

公开(公告)日：2021-03-23

申请号：US16894860

申请日：2020-06-07

申请人： MEDIATEK INC.

发明人： Wei-Hsin Tseng

IPC分类号： H03M1/66 ,  H03M1/74 ,  H03M1/06 ,  H03M3/00

摘要： A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.

公开(公告)号：US20200287574A1

公开(公告)日：2020-09-10

申请号：US16776513

申请日：2020-01-30

申请人： MEDIATEK INC.

发明人： Chieh-Hsun Hsiao ,  Ming-Chou Wu ,  Wen-Chang Lee ,  Narayanan Baskaran ,  Wei-Hsin Tseng ,  Jenwei Ko ,  Po-Sen Tseng ,  Hsin-Hung Chen ,  Chih-Yuan Lin ,  Caiyi Wang

IPC分类号： H04B1/00

摘要： A transmission interface between at least a master module and a slave module is proposed. The transmission interface includes a predetermined number of physical transmission medium(s). Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated, and the predetermined number is not smaller than a number of intermediate frequency (IF) stream(s) to be transmitted.

公开(公告)号：US20170085349A1

公开(公告)日：2017-03-23

申请号：US15165088

申请日：2016-05-26

申请人： MediaTek Inc.

发明人： Stacy Ho ,  Wei-Hsin Tseng

IPC分类号： H04L5/00 ,  H03M3/00 ,  H03M1/06 ,  H04B1/12 ,  H03M1/46

CPC分类号： H04L5/0041 ,  H03M1/0617 ,  H03M1/466 ,  H03M3/406 ,  H03M3/41 ,  H03M3/426 ,  H03M3/47 ,  H04B1/0075 ,  H04B1/123 ,  H04L5/001 ,  H04L27/2647

摘要： Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.