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1.发明申请METHOD FOR PERFORMING LOOP UNROLLED DECISION FEEDBACK EQUALIZATION IN AN ELECTRONIC DEVICE WITH AID OF VOLTAGE FEEDFORWARD, AND ASSOCIATED APPARATUS 有权在具有电压补偿的电子设备中执行环路未决决策反馈均衡的方法和相关设备公开(公告)号：US20160065397A1
公开(公告)日：2016-03-03
申请号：US14737513
申请日：2015-06-12
Applicant: MEDIATEK INC.
Inventor： Tsung-Hsin Chou , Chih-Hsien Lin , Huai-Te Wang , Bo-Jiun Chen , Yan-Bin Luo
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885 , H04L2025/03484 , H04L2025/0349 , H04L2025/03777 , H04L2025/03808
Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided. The method includes: receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in an electronic device, and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver; broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward comparators in the DFE receiver; utilizing the comparators to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate comparison results; and selectively adjusting the tap control signal and the offset control signal according to the comparison results, to optimize the DFE information respectively corresponding to the tap control signal and the offset control signal, respectively.
Abstract translation: 提供了一种用于执行循环展开的判决反馈均衡（DFE）和相关联的装置的方法。 该方法包括：从电子设备中的DFE接收机的数字域接收抽头控制信号和偏移控制信号，并且在DFE的模拟域中产生分别对应于抽头控制信号和偏移控制信号的DFE信息 接收器 将分别对应于抽头控制信号和偏移控制信号的DFE信息广播到DFE接收机中的比较器; 利用比较器根据分别对应于抽头控制信号和偏移控制信号的DFE信息执行比较操作，以产生比较结果; 并且根据比较结果选择性地调整抽头控制信号和偏移控制信号，分别优化分别对应于抽头控制信号和偏移控制信号的DFE信息。
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公开(公告)号：US09590595B2
公开(公告)日：2017-03-07
申请号：US14825149
申请日：2015-08-12
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
IPC: H03K17/10 , H03K3/012 , H03K19/0185 , H04L25/03 , H03K19/0175
CPC classification number: H03K3/012 , H03K19/017509 , H03K19/018528 , H03K19/018585 , H04L25/03076
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.
Abstract translation: 提供了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号，其中 一对差分输出端子具有第一输出端子和第二输出端子; 耦合到所述一对差分输出端子的至少一个电流模式驱动单元，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及从所述第一输出端子和所述第二输出端子中的另一个接收电流 终端根据第一位; 以及耦合到所述一对差分输出端子的至少一个电压模式驱动单元，用于根据所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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3.发明授权Method for performing loop unrolled decision feedback equalization in an electronic device with aid of voltage feedforward, and associated apparatus 有权一种借助于电压前馈在电子设备中执行循环展开判决反馈均衡的方法，以及相关联的装置公开(公告)号：US09479365B2
公开(公告)日：2016-10-25
申请号：US14737513
申请日：2015-06-12
Applicant: MEDIATEK INC.
Inventor： Tsung-Hsin Chou , Chih-Hsien Lin , Huai-Te Wang , Bo-Jiun Chen , Yan-Bin Luo
CPC classification number: H04L25/03057 , H04L25/03885 , H04L2025/03484 , H04L2025/0349 , H04L2025/03777 , H04L2025/03808
Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided. The method includes: receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in an electronic device, and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver; broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward comparators in the DFE receiver; utilizing the comparators to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate comparison results; and selectively adjusting the tap control signal and the offset control signal according to the comparison results, to optimize the DFE information respectively corresponding to the tap control signal and the offset control signal, respectively.
Abstract translation: 提供了一种用于执行循环展开的判决反馈均衡（DFE）和相关联的装置的方法。 该方法包括：从电子设备中的DFE接收机的数字域接收抽头控制信号和偏移控制信号，并且在DFE的模拟域中产生分别对应于抽头控制信号和偏移控制信号的DFE信息 接收器 将分别对应于抽头控制信号和偏移控制信号的DFE信息广播到DFE接收机中的比较器; 利用比较器根据分别对应于抽头控制信号和偏移控制信号的DFE信息执行比较操作，以产生比较结果; 并且根据比较结果选择性地调整抽头控制信号和偏移控制信号，分别优化分别对应于抽头控制信号和偏移控制信号的DFE信息。
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Patent Agency Ranking
4.发明申请公开(公告)号：US20160191037A1
公开(公告)日：2016-06-30
申请号：US14822913
申请日：2015-08-11
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
IPC: H03K17/10
CPC classification number: H03K17/10 , H04L25/0272 , H04L25/0282 , H04L25/4906
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.
Abstract translation: 公开了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号 ，其中所述一对差分输出端子具有第一输出端子和第二输出端子; 电流模式驱动单元，耦合到所述一对差分输出端子，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及根据所述第一输出端子和所述第二输出端子中的另一个接收所述电流， 到第一位 以及耦合到所述一对差分输出端子的电压模式驱动单元，用于根据至少所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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5.发明申请METHOD FOR PERFORMING DATA SAMPLING CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS 有权在电子设备中执行数据采样控制的方法及相关设备公开(公告)号：US20160056980A1
公开(公告)日：2016-02-25
申请号：US14740264
申请日：2015-06-16
Applicant: MEDIATEK INC.
Inventor： Huai-Te Wang , Tsung-Hsin Chou , Chih-Hsien Lin , Bo-Jiun Chen , Yan-Bin Luo
CPC classification number: H04L25/03057 , H03L7/087 , H03L7/091 , H03L7/095 , H03L7/099 , H04L7/0025 , H04L7/0331
Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.
Abstract translation: 提供了一种在电子设备和相关设备中执行数据采样控制的方法，其中该方法包括以下步骤：检测电子设备中的判决反馈均衡器（DFE）接收机的接收信号的数据模式是否匹配 预定数据模式，以选择性地触发DFE接收机的数据采样时移配置; 并且当触发数据采样时移配置时，利用相移时钟而不是与DFE接收机的正常配置对应的正常时钟作为DFE接收机中的边缘采样器的边缘采样器时钟来锁定到边缘 接收信号的定时，并且分别控制相移时钟和正常时钟以具有不同的相位，以移位DFE接收机的数据采样时间，以便在DFE接收机中执行数据采样。
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6.发明授权公开(公告)号：US09590610B2
公开(公告)日：2017-03-07
申请号：US14822913
申请日：2015-08-11
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
CPC classification number: H03K17/10 , H04L25/0272 , H04L25/0282 , H04L25/4906
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.
Abstract translation: 公开了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号 ，其中所述一对差分输出端子具有第一输出端子和第二输出端子; 电流模式驱动单元，耦合到所述一对差分输出端子，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及根据所述第一输出端子和所述第二输出端子中的另一个接收所述电流， 到第一位 以及耦合到所述一对差分输出端子的电压模式驱动单元，用于根据至少所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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7.发明授权Method for performing data sampling control in an electronic device, and associated apparatus 有权用于在电子设备中执行数据采样控制的方法和相关联的设备公开(公告)号：US09379921B2
公开(公告)日：2016-06-28
申请号：US14740264
申请日：2015-06-16
Applicant: MEDIATEK INC.
Inventor： Huai-Te Wang , Tsung-Hsin Chou , Chih-Hsien Lin , Bo-Jiun Chen , Yan-Bin Luo
CPC classification number: H04L25/03057 , H03L7/087 , H03L7/091 , H03L7/095 , H03L7/099 , H04L7/0025 , H04L7/0331
Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.
Abstract translation: 提供了一种在电子设备和相关设备中执行数据采样控制的方法，其中该方法包括以下步骤：检测电子设备中的判决反馈均衡器（DFE）接收机的接收信号的数据模式是否匹配 预定数据模式，以选择性地触发DFE接收机的数据采样时移配置; 并且当触发数据采样时移配置时，利用相移时钟而不是与DFE接收机的正常配置对应的正常时钟作为DFE接收机中的边缘采样器的边缘采样器时钟来锁定到边缘 接收信号的定时，并且分别控制相移时钟和正常时钟以具有不同的相位，以移位DFE接收机的数据采样时间，以便在DFE接收机中执行数据采样。
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公开(公告)号：US20160204768A1
公开(公告)日：2016-07-14
申请号：US14825149
申请日：2015-08-12
Applicant: Mediatek Inc.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
CPC classification number: H03K3/012 , H03K19/017509 , H03K19/018528 , H03K19/018585 , H04L25/03076
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.
Abstract translation: 提供了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号，其中 一对差分输出端子具有第一输出端子和第二输出端子; 耦合到所述一对差分输出端子的至少一个电流模式驱动单元，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及从所述第一输出端子和所述第二输出端子中的另一个接收电流 终端根据第一位; 以及耦合到所述一对差分输出端子的至少一个电压模式驱动单元，用于根据所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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