公开(公告)号：US20100153747A1

公开(公告)日：2010-06-17

申请号：US12333822

申请日：2008-12-12

申请人： Mehdi Asnaashari ,  Robin Sarno

发明人： Mehdi Asnaashari ,  Robin Sarno

IPC分类号： H04L9/06

CPC分类号： H04L9/28 ,  H04L9/0631 ,  H04L9/0637 ,  H04L2209/12

摘要： The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate.

摘要翻译： 本公开包括用于并行加密/解密的方法和装置。 在一个或多个实施例中，加密/解密装置包括在输入逻辑电路和输出逻辑电路之间并联布置的输入逻辑电路，输出逻辑电路和多个加密/解密电路。 例如，每个加密/解密电路能够以加密/解密速率处理数据，并且加密/解密电路的数量可以等于或大于接口吞吐速率除以加密/解密速率。

公开(公告)号：US08355499B2

公开(公告)日：2013-01-15

申请号：US12333822

申请日：2008-12-12

申请人： Mehdi Asnaashari ,  Robin Sarno

发明人： Mehdi Asnaashari ,  Robin Sarno

IPC分类号： H04L9/28

CPC分类号： H04L9/28 ,  H04L9/0631 ,  H04L9/0637 ,  H04L2209/12

摘要： The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate.

公开(公告)号：US09009357B2

公开(公告)日：2015-04-14

申请号：US12109284

申请日：2008-04-24

申请人： Mehdi Asnaashari

发明人： Mehdi Asnaashari

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06F9/445

CPC分类号： G06F8/665 ,  G06F3/0605 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0679 ,  G06F8/65 ,  G06F8/654 ,  G06F9/4411 ,  G06F21/33 ,  G06F21/572 ,  G06F2221/031 ,  G06F2221/2153

摘要： Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller, where the controller operates in accordance with the device firmware. The controller determines whether or not the device firmware can be updated with new firmware at least partially based on whether or not the new firmware meets a criterion related to a configuration profile of the device firmware.

摘要翻译： 公开了用于更新固件的数据存储设备和方法。 例如，一个这样的数据存储设备包括设备固件和控制器，其中控制器根据设备固件进行操作。 至少部分地基于新固件是否满足与设备固件的配置简档相关的标准，控制器确定是否可以用新固件更新设备固件。

公开(公告)号：US08468417B2

公开(公告)日：2013-06-18

申请号：US12388305

申请日：2009-02-18

申请人： Mehdi Asnaashari ,  Ronald Yamada ,  Siamack Nemazie ,  Jui-Yao (“Ray”) Yang

发明人： Mehdi Asnaashari ,  Ronald Yamada ,  Siamack Nemazie ,  Jui-Yao (“Ray”) Yang

IPC分类号： H03M13/00

CPC分类号： G06F11/1048 ,  G06F11/10 ,  G06F11/1004 ,  G06F13/28 ,  G06F21/64 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/13 ,  H03M13/29

摘要： The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

公开(公告)号：US08276042B2

公开(公告)日：2012-09-25

申请号：US12364900

申请日：2009-02-03

申请人： Mehdi Asnaashari ,  Yu-Song Liao ,  Siamack Nemazie

发明人： Mehdi Asnaashari ,  Yu-Song Liao ,  Siamack Nemazie

IPC分类号： G06F11/00

CPC分类号： G11C16/06 ,  G06F11/1012 ,  G11C29/04 ,  G11C2029/0411

摘要： The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.

摘要翻译： 本公开包括用于操作半导体存储器的方法，设备，模块和系统。 许多方法实施例包括从对应于数据扇区的存储器单元读取数据，确定处于未擦除状态的存储单元的数量，以及如果未擦除状态的存储单元的数量小于 或等于可由ECC引擎校正的错误数量，确定扇区被擦除。

公开(公告)号：US08260973B2

公开(公告)日：2012-09-04

申请号：US13242535

申请日：2011-09-23

申请人： Mehdi Asnaashari ,  Yu-Song Liao ,  Jui-Yao Yang ,  Siamack Nemazie

发明人： Mehdi Asnaashari ,  Yu-Song Liao ,  Jui-Yao Yang ,  Siamack Nemazie

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0688 ,  G06F13/161 ,  G06F13/28

摘要： The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

摘要翻译： 本公开包括用于存储器控制器的方法和装置。 在一个或多个实施例中，存储器控制器包括多个后端通道，以及通信地耦合到多个后端通道的命令队列。 命令队列配置为保存从主机接收的主机命令。 电路被配置为至少响应于命令队列中的主机命令的数量生成多个后端命令，并且将后端命令的数量分配给多个后端信道的数量。

公开(公告)号：US20100229004A1

公开(公告)日：2010-09-09

申请号：US12397149

申请日：2009-03-03

申请人： Mehdi Asnaashari

发明人： Mehdi Asnaashari

IPC分类号： G06F12/14 ,  G06F12/00

CPC分类号： G06F12/1408 ,  G06F21/78

摘要： Security parameters used to encrypt data stored on a storage device may be protected using embodiments of systems and methods described herein. During a resize operation, data stored on a memory unit in the storage device may be altered prior to communicating an updated partition size to a host computer. In some examples, data is altered prior to storing the updated partition sizes in the storage device. In this manner, a host system may not receive the updated partition sizes until after the data is altered. Altering data may avoid exposure encrypted data, information about one or more security parameters used to encrypt data on the memory unit or decrypt data retrieved from the memory unit, or combinations thereof.

摘要翻译： 可以使用本文所述的系统和方法的实施例来保护用于加密存储在存储设备上的数据的安全参数。 在调整大小操作期间，可以在将更新的分区大小传送到主计算机之前改变存储在存储设备中的存储器单元上的数据。 在一些示例中，在将更新的分区大小存储在存储设备中之前，更改数据。 以这种方式，在更改数据之后，主机系统可能不会接收到更新的分区大小。 更改数据可以避免暴露加密数据，关于用于加密存储器单元上的数据的一个或多个安全参数的信息或者解密从存储器单元检索的数据的信息，或其组合。

公开(公告)号：US20100180105A1

公开(公告)日：2010-07-15

申请号：US12351206

申请日：2009-01-09

申请人： Mehdi Asnaashari

发明人： Mehdi Asnaashari

IPC分类号： G06F9/318

CPC分类号： G06F13/1642 ,  G06F13/1631

摘要： The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the modified commands.

摘要翻译： 本公开包括用于修改命令的方法，设备，模块和系统。 一个设备实施例包括包括信道的存储器控​​制器，其中信道包括被配置为保存命令的命令队列，以及被配置为修改队列中的至少多个命令并执行修改的命令的电路。

公开(公告)号：US20100023747A1

公开(公告)日：2010-01-28

申请号：US11938739

申请日：2007-11-12

申请人： Mehdi Asnaashari ,  Ruchirkumar D. Shah ,  Sylvain Prevost ,  Ksheerabdhi Krishna

发明人： Mehdi Asnaashari ,  Ruchirkumar D. Shah ,  Sylvain Prevost ,  Ksheerabdhi Krishna

IPC分类号： H04L9/32 ,  G06K19/073 ,  G06F12/14

CPC分类号： H04L9/3234 ,  G06F21/34 ,  G06F21/77 ,  G06F21/79 ,  G06Q20/3563

摘要： A storage device contains a smart-card device and a memory device, which is connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data. The memory device may also be used to store data or instructions for use by the smart-card device. The controller includes a security engine that uses critical security parameters stored in, and received from, the smart-card device. The critical security parameters may be sent to the controller in a manner that protects them from being discovered. The critical security parameters may be encryption and/or decryption keys that may encrypt data written to the memory device and/or decrypt data read from the memory device, respectively. Data and instructions used by the smart-card device may therefore stored in the memory device in encrypted form.

摘要翻译： 存储设备包含智能卡设备和连接到控制器的存储设备。 存储装置可以以与常规智能卡装置相同的方式使用，或者可以用于存储相对大量的数据。 存储器装置还可以用于存储由智能卡装置使用的数据或指令。 控制器包括使用存储在智能卡设备中并从智能卡设备接收的关键安全参数的安全引擎。 关键的安全参数可以以保护它们免受发现的方式发送到控制器。 关键的安全参数可以是加密和/或解密密钥，其可以分别加密写入存储器件的数据和/或解密从存储器件读取的数据。 因此，智能卡设备使用的数据和指令可以以加密形式存储在存储设备中。

公开(公告)号：US20090125643A1

公开(公告)日：2009-05-14

申请号：US11938775

申请日：2007-11-12

申请人： Sylvain Prevost ,  Ksheerabdhi Krishna ,  Ruchirkumar D. Shah ,  Mehdi Asnaashari

发明人： Sylvain Prevost ,  Ksheerabdhi Krishna ,  Ruchirkumar D. Shah ,  Mehdi Asnaashari

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G06F3/0644 ,  G06F3/0623 ,  G06F3/0632 ,  G06F3/0679 ,  G06F21/78 ,  G06F2221/2153

摘要： A system and method to control a device having at least one configurable parameter. Enumerating the device as a first peripheral device and as a second peripheral device wherein the first peripheral device corresponds to a first microcontroller connected to a storage medium and the second peripheral device corresponds to a second microcontroller. Controlling the at least one configurable parameter of the first microcontroller with respect to the storage medium by the second microcontroller. On initialization of the device, transmitting the at least one configurable parameter from the second microcontroller to the first microcontroller. Other systems and methods are disclosed.

摘要翻译： 一种用于控制具有至少一个可配置参数的设备的系统和方法。 将设备列举为第一外围设备和第二外围设备，其中第一外围设备对应于连接到存储介质的第一微控制器，而第二外围设备对应于第二微控制器。 通过第二微控制器控制第一微控制器相对于存储介质的至少一个可配置参数。 在初始化装置时，将至少一个可配置参数从第二微控制器发送到第一微控制器。 公开了其它系统和方法。