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    Efficient use of buffer space in a network switch
    1.
    发明授权
    Efficient use of buffer space in a network switch 有权

    公开(公告)号：US10387074B2

    公开(公告)日：2019-08-20

    申请号：US15161316

    申请日：2016-05-23

    Applicant: Mellanox Technologies TLV Ltd.

    Inventor： Roy Kriss ,  Barak Gafni ,  George Elias ,  Eran Rubinstein ,  Shachar Bar Tikva

    IPC: H04L12/933 ,  G06F3/06 ,  H04L12/935 ,  H04L12/861

    Abstract: Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A memory is coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.

    Memory-efficient handling of multicast traffic
    2.
    发明授权
    Memory-efficient handling of multicast traffic 有权

    公开(公告)号：US10015112B2

    公开(公告)日：2018-07-03

    申请号：US14961923

    申请日：2015-12-08

    Applicant: Mellanox Technologies TLV Ltd.

    Inventor： Amir Roitshtein ,  Niv Aibester ,  Barak Gafni ,  George Elias

    IPC: H04L12/931 ,  H04L12/861 ,  H04L12/741

    CPC classification number: H04L49/201 ,  H04L45/745 ,  H04L49/205 ,  H04L49/9005

    Abstract: Communication apparatus includes multiple interfaces connected to a packet data network. A memory is coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a multicast packet through an ingress interface, to identify a number of the egress interfaces through which respective copies of the multicast packet are to be transmitted, to allocate a space in the buffer for storage of a single copy of the multicast packet, to replicate and transmit multiple copies of the stored copy of the multicast packet through the egress interfaces, to maintain a count of the replicated copies that have been transmitted, and when the count reaches the identified number, to release the allocated space in the buffer.

    Flexible Allocation of Packet Buffers
    5.
    发明申请
    Flexible Allocation of Packet Buffers 审中-公开

    公开(公告)号：US20170201469A1

    公开(公告)日：2017-07-13

    申请号：US14994164

    申请日：2016-01-13

    Applicant: MELLANOX TECHNOLOGIES TLV LTD.

    Inventor： George Elias ,  Barak Gafni ,  Shachar Bar Tikva ,  Roy Kriss ,  Eran Rubinstein

    IPC: H04L12/861 ,  H04L12/26 ,  H04L12/863

    CPC classification number: H04L43/0817 ,  H04L49/108 ,  H04L49/254

    Abstract: Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A single memory array is coupled to the ports and configured to contain both a respective headroom allocation for each ingress port and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to adjustably allocate to each ingress port a respective volume of memory within the single memory array to serve as the respective headroom allocation, and to queue the data packets in the multiple queues in the single memory array for transmission through the egress ports.

    Reusing Switch Ports for External Buffer Network
    6.
    发明申请
    Reusing Switch Ports for External Buffer Network 审中-公开

    公开(公告)号：US20200287846A1

    公开(公告)日：2020-09-10

    申请号：US16294958

    申请日：2019-03-07

    Applicant: MELLANOX TECHNOLOGIES TLV LTD.

    Inventor： George Elias ,  Gil Levy ,  Liron Mula ,  Aviv Kfir ,  Benny Koren ,  Sagi Kuks

    IPC: H04L12/861 ,  H04L12/935

    Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

    LOW-COMPLEXITY MEASUREMENT OF PACKET TRAVERSAL TIME IN NETWORK ELEMENT
    8.
    发明申请
    LOW-COMPLEXITY MEASUREMENT OF PACKET TRAVERSAL TIME IN NETWORK ELEMENT 审中-公开

    公开(公告)号：US20180152365A1

    公开(公告)日：2018-05-31

    申请号：US15361528

    申请日：2016-11-28

    Applicant: Mellanox Technologies TLV Ltd.

    Inventor： Oded Belfer ,  George Elias ,  Gil Levy

    IPC: H04L12/26

    CPC classification number: H04L43/0858 ,  H04L43/106

    Abstract: A network element includes multiple interfaces and circuitry. The interfaces are configured to connect to a communication system. The circuitry is configured to receive via an ingress interface a packet that includes an Error Detection Code (EDC) field including an input EDC value, to determine an input timestamp indicative of a time-of-arrival of the received packet at the network element, and overwrite at least part of the input EDC value in the EDC field of the packet with the input timestamp, to estimate for the packet a traversal latency between reception at the ingress interface and transmission via a selected egress interface, based at least on the input timestamp, and to produce a deliverable version of the packet by writing an output EDC value to the EDC field, and send the deliverable version of the packet via the selected egress interface.

    Generating high-speed test traffic in a network switch
    10.
    发明申请
    Generating high-speed test traffic in a network switch 审中-公开

    公开(公告)号：US20170366442A1

    公开(公告)日：2017-12-21

    申请号：US15186557

    申请日：2016-06-20

    Applicant: Mellanox Technologies TLV Ltd.

    Inventor： Amiad Marelli ,  George Elias ,  Itamar Rabenstein ,  Miriam Menes ,  Ido Bukspan

    IPC: H04L12/26 ,  H04L12/18 ,  H04L12/947

    CPC classification number: H04L43/50 ,  H04L12/1854 ,  H04L43/106 ,  H04L49/25

    Abstract: Communication apparatus includes multiple interfaces connected to a packet data network, and a memory coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a test packet through an ingress interface of the apparatus, to allocate a space in the buffer for storage of a single copy of the test packet, to replicate and transmit sequentially multiple copies of the stored copy of the test packet through a designated egress interface, to receive an indication of a number of copies of the test packet that are to be transmitted, and responsively to the indication, to terminate replication of the test packet and release the allocated space in the buffer.

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