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公开(公告)号：US20150279836A1
公开(公告)日：2015-10-01
申请号：US14231849
申请日：2014-04-01
申请人： Michael A. Stockinger , Wenzhong Zhang , Xu Zhang
发明人： Michael A. Stockinger , Wenzhong Zhang , Xu Zhang
IPC分类号： H01L27/02
CPC分类号： H01L27/0285 , H01L27/0274 , H01L29/1087 , H01L29/4238 , H01L29/78
摘要： An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.
摘要翻译： 公开了一种集成电路电气保护装置，其包括半导体衬底和划分成多个段的多个晶体管指状物。 通过在由相邻段共享的源极/漏极区域内彼此间隔开的区域，这些区段彼此区分开。
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公开(公告)号：US09202808B2
公开(公告)日：2015-12-01
申请号：US14231849
申请日：2014-04-01
申请人： Michael A. Stockinger , Wenzhong Zhang , Xu Zhang
发明人： Michael A. Stockinger , Wenzhong Zhang , Xu Zhang
IPC分类号： H01L27/02
CPC分类号： H01L27/0285 , H01L27/0274 , H01L29/1087 , H01L29/4238 , H01L29/78
摘要： An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.
摘要翻译： 公开了一种集成电路电气保护装置，其包括半导体衬底和划分成多个段的多个晶体管指状物。 通过在由相邻段共享的源极/漏极区域内彼此间隔开的区域，这些区段彼此区分开。
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公开(公告)号：US20110316610A1
公开(公告)日：2011-12-29
申请号：US12824991
申请日：2010-06-28
IPC分类号： H03K17/687 , H03K17/00
CPC分类号： H03K17/102
摘要： A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.
摘要翻译： 传输门电路包括具有第一开关装置的第一传输门，第一开关装置与第二传输门串联，具有第二开关装置，以及控制电路，其将第一传输门和第二传输门置于导通状态 提供穿过第一传输门和第二传输门的导电路径。 当第一端子的电压高于第一电压电平并且在第一和第二开关装置中的至少一个的安全工作电压区域之外时，第一开关装置保持在其安全工作电压区域内，并且第二开关装置保持在 其安全工作电压面积。
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公开(公告)号：US08228109B2
公开(公告)日：2012-07-24
申请号：US12824991
申请日：2010-06-28
IPC分类号： H03K5/08
CPC分类号： H03K17/102
摘要： A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.
摘要翻译： 传输门电路包括具有第一开关装置的第一传输门，第一开关装置与第二传输门串联，具有第二开关装置，以及控制电路，其将第一传输门和第二传输门置于导通状态 提供穿过第一传输门和第二传输门的导电路径。 当第一端子的电压高于第一电压电平并且在第一和第二开关装置中的至少一个的安全工作电压区域之外时，第一开关装置保持在其安全工作电压区域内，并且第二开关装置保持在 其安全工作电压面积。
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公开(公告)号：US09652577B2
公开(公告)日：2017-05-16
申请号：US14505237
申请日：2014-10-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5072
摘要： This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.
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6.发明申请公开(公告)号：US20160098510A1
公开(公告)日：2016-04-07
申请号：US14505237
申请日：2014-10-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5072
摘要： This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.
摘要翻译： 本公开描述了创建预先标记的电路元件对象的库的方法，并且使用预先标记的电路元件对象库来设计和制造集成电路。 电路元件对象中的每一个都被“预先标记”，并且包括对电路元件对象中的每个端子具有独立的预分配电压值的嵌入式电压标记。 当电路设计者在原理图设计中插入预先标记的电路元件对象时，设计工具确定电路元件对象端子的预分配电压值中的每一个是否与它们所连接的相应网络匹配。 当电路设计人员在原理图设计中完成包括有效网络的原理图设计时，设计工具将从原理图设计生成布局设计。 当布局设计通过验证测试时，设计工具又会从布局设计中生成掩模层数据。
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公开(公告)号：US09293451B2
公开(公告)日：2016-03-22
申请号：US13682558
申请日：2012-11-20
CPC分类号： H01L27/0277 , H01L27/0629
摘要： An integrated circuit electrical protection device includes a semiconductor substrate, and first, second, and third doped regions of a first polarity in the semiconductor substrate. The first and second doped regions are separated from one another by a first body region having a second polarity and the second and third doped regions are separated from one another by a second body region having the second polarity. The first and second polarities are different from one another. A fourth doped region of the second polarity directly abutting and in contact with the third doped region. A first gate structure is formed over the first body region between the first and second doped regions. A second gate structure is formed over the second body region between the second and third doped regions.
摘要翻译： 集成电路电气保护装置包括半导体衬底和半导体衬底中具有第一极性的第一，第二和第三掺杂区域。 第一和第二掺杂区域通过具有第二极性的第一体区彼此分离，并且第二和第三掺杂区域通过具有第二极性的第二体区彼此分离。 第一和第二极性彼此不同。 第二极性的第四掺杂区直接邻接并与第三掺杂区接触。 在第一和第二掺杂区域之间的第一体区上形成第一栅极结构。 第二栅极结构形成在第二和第三掺杂区域之间的第二体区上。
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公开(公告)号：US09268972B2
公开(公告)日：2016-02-23
申请号：US14246132
申请日：2014-04-06
CPC分类号： G06F21/86 , G01D4/004 , G01R22/066 , H04Q9/14
摘要： A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
摘要翻译： 篡改检测器具有通过篡改检测接口连接到篡改检测端口的篡改检测逻辑。 实时时钟（RTC）提供时钟信号并具有电池。 处理器由处于供电操作模式的外部电源供电并具有断电模式。 在唤醒配置中，特定I / O端口上的唤醒信号会从断电模式唤醒外部电源，以便在电池电源不可用时向RTC和篡改检测接口供电。 篡改检测端口在电池没有ESD问题的情况下即使卸下或放电也能继续工作。 特定的I / O端口可以被配置为被动篡改检测。
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公开(公告)号：US09236372B2
公开(公告)日：2016-01-12
申请号：US13193855
申请日：2011-07-29
CPC分类号： H01L27/0255
摘要： An integrated circuit ESD protection circuit (270) is formed with a combination device consisting of a gated diode (271) and an output buffer MOSFET (272) where the body tie fingers of a first conductivity type (307) are formed in the substrate (301, 302) and isolated from the drain regions of a second conductivity type (310) using a plurality of diode poly fingers (231, 232) which are interleaved with a plurality of poly gate fingers (204, 205) forming the output buffer MOSFET (272).
摘要翻译： 集成电路ESD保护电路（270）由具有门控二极管（271）和输出缓冲MOSFET（272）组成的组合装置形成，其中第一导电类型（307）的主体连接指形成在衬底中 使用与形成输出缓冲MOSFET的多个多晶硅栅极（204,205）交错的多个二极管多指（231,232）与第二导电类型（310）的漏极区隔离， （272）。
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公开(公告)号：US20150286846A1
公开(公告)日：2015-10-08
申请号：US14246132
申请日：2014-04-06
CPC分类号： G06F21/86 , G01D4/004 , G01R22/066 , H04Q9/14
摘要： A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
摘要翻译： 篡改检测器具有通过篡改检测接口连接到篡改检测端口的篡改检测逻辑。 实时时钟（RTC）提供时钟信号并具有电池。 处理器由处于供电操作模式的外部电源供电并具有断电模式。 在唤醒配置中，特定I / O端口上的唤醒信号会从断电模式唤醒外部电源，以便在电池电源不可用时向RTC和篡改检测接口供电。 篡改检测端口在电池没有ESD问题的情况下即使卸下或放电也能继续工作。 特定的I / O端口可以被配置为被动篡改检测。
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