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公开(公告)号：US09031736B2
公开(公告)日：2015-05-12
申请号：US14150738
申请日：2014-01-08
申请人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
发明人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
IPC分类号： G06F7/00 , G07C5/00 , G01P15/125 , H02M1/36 , H04L7/04
CPC分类号： G07C5/00 , G01P15/125 , H02M1/36 , H04L7/044
摘要： A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.
摘要翻译： 用于对从传感器发送并由接收器接收的数据消息进行诊断检查的系统包括接收机时钟计数器，预分频器计数器，校准脉冲检测器，半字节计数器和计算器。 系统接收从传感器发送的第一和第二数据消息。 第一和第二数据消息的第一和第二校准脉冲的分别为第一和第二数据消息的长度的脉冲宽度使用接收器时钟tick，预分频器和半字节计数器基于经补偿的接收机时钟信号来测量。 此后，使用计算器比较第一和第二校准脉冲的脉冲宽度以及第一和第二数据消息的长度以执行诊断检查。
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公开(公告)号：US08689357B2
公开(公告)日：2014-04-01
申请号：US13475947
申请日：2012-05-19
申请人： Mohit Arora , Rakesh Pandey , Pushkar Sareen , Prashant Bhargava
发明人： Mohit Arora , Rakesh Pandey , Pushkar Sareen , Prashant Bhargava
IPC分类号： G06F21/00
CPC分类号： G06F21/72 , G06F21/755
摘要： A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.
摘要翻译： 篡改检测器具有用于连接到篡改检测电路的端部的输入和输出引脚和由时钟信号定时的对应的一组线性反馈移位寄存器（LFSR），用于产生作为种子值的函数的伪随机编码检测信号，以及 由反馈抽头定义的生成多项式。 比较器将从检测电路接收的信号与编码的检测信号进行比较。 复用器将选择性地从LFSR向编码的检测信号提供给输出引脚和比较器。 控制器改变伪随机编码检测信号的不同周期值的种子值。 控制器还控制生成多项式和针对伪随机编码检测信号的不同周期值的时钟信号的频率。
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公开(公告)号：US09268972B2
公开(公告)日：2016-02-23
申请号：US14246132
申请日：2014-04-06
CPC分类号： G06F21/86 , G01D4/004 , G01R22/066 , H04Q9/14
摘要： A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
摘要翻译： 篡改检测器具有通过篡改检测接口连接到篡改检测端口的篡改检测逻辑。 实时时钟（RTC）提供时钟信号并具有电池。 处理器由处于供电操作模式的外部电源供电并具有断电模式。 在唤醒配置中，特定I / O端口上的唤醒信号会从断电模式唤醒外部电源，以便在电池电源不可用时向RTC和篡改检测接口供电。 篡改检测端口在电池没有ESD问题的情况下即使卸下或放电也能继续工作。 特定的I / O端口可以被配置为被动篡改检测。
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公开(公告)号：US20150286846A1
公开(公告)日：2015-10-08
申请号：US14246132
申请日：2014-04-06
CPC分类号： G06F21/86 , G01D4/004 , G01R22/066 , H04Q9/14
摘要： A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
摘要翻译： 篡改检测器具有通过篡改检测接口连接到篡改检测端口的篡改检测逻辑。 实时时钟（RTC）提供时钟信号并具有电池。 处理器由处于供电操作模式的外部电源供电并具有断电模式。 在唤醒配置中，特定I / O端口上的唤醒信号会从断电模式唤醒外部电源，以便在电池电源不可用时向RTC和篡改检测接口供电。 篡改检测端口在电池没有ESD问题的情况下即使卸下或放电也能继续工作。 特定的I / O端口可以被配置为被动篡改检测。
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公开(公告)号：US09152430B2
公开(公告)日：2015-10-06
申请号：US13910092
申请日：2013-06-04
CPC分类号： G06F9/4406 , G06F1/24 , G06F1/30 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F9/4401 , G06F11/1417
摘要： A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.
摘要翻译： 微控制器包括具有内部参考时钟的时钟发生器，建立操作模式的系统模式控制器，具有内部时钟和非易失性选项寄存器的闪存，以及耦合到系统模式控制器的引导模式选择逻辑电路， 闪存。 逻辑电路输出指示微控制器以非常低功率运行（VLPR）模式或RUN模式引导的引导模式选择信号。 系统模式控制器响应进入VLPR或RUN模式。 闪速存储器在VLPR模式下校准闪存之前，以及在RUN模式下闪存初始化之前，会旁路和禁用其内部时钟。 闪存随后根据内部参考时钟的输出使用外部时钟信号。
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公开(公告)号：US20140359264A1
公开(公告)日：2014-12-04
申请号：US13910092
申请日：2013-06-04
IPC分类号： G06F9/44
CPC分类号： G06F9/4406 , G06F1/24 , G06F1/30 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F9/4401 , G06F11/1417
摘要： A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.
摘要翻译： 微控制器包括具有内部参考时钟的时钟发生器，建立操作模式的系统模式控制器，具有内部时钟和非易失性选项寄存器的闪存，以及耦合到系统模式控制器的引导模式选择逻辑电路， 闪存。 逻辑电路输出指示微控制器以非常低功率运行（VLPR）模式或RUN模式引导的引导模式选择信号。 系统模式控制器响应进入VLPR或RUN模式。 闪速存储器在VLPR模式下校准闪存之前，以及在RUN模式下闪存初始化之前，会旁路和禁用其内部时钟。 闪存随后根据内部参考时钟的输出使用外部时钟信号。
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公开(公告)号：US08896086B1
公开(公告)日：2014-11-25
申请号：US13905150
申请日：2013-05-30
申请人： Mohit Arora , Prashant Bhargava , Rishi Bhooshan
发明人： Mohit Arora , Prashant Bhargava , Rishi Bhooshan
CPC分类号： G06F21/86 , G06F2221/2143 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.
摘要翻译： 用于产生表示篡改集成电路（IC）的一个或多个电路的篡改检测信号的系统包括篡改检测模块和连接到篡改检测模块并且以绕组配置布置以形成线网的线对 。 线网放置在与电路预定距离的位置。 篡改检测模块生成并提供串行比特流到线对，用于通过外部探针检测金属丝网中的突破。
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公开(公告)号：US20140121886A1
公开(公告)日：2014-05-01
申请号：US14150738
申请日：2014-01-08
申请人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
发明人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
IPC分类号： G07C5/00
CPC分类号： G07C5/00 , G01P15/125 , H02M1/36 , H04L7/044
摘要： A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.
摘要翻译： 用于对从传感器发送并由接收器接收的数据消息进行诊断检查的系统包括接收机时钟计数器，预分频器计数器，校准脉冲检测器，半字节计数器和计算器。 系统接收从传感器发送的第一和第二数据消息。 第一和第二数据消息的第一和第二校准脉冲的分别为第一和第二数据消息的长度的脉冲宽度使用接收器时钟tick，预分频器和半字节计数器基于经补偿的接收机时钟信号来测量。 此后，使用计算器比较第一和第二校准脉冲的脉冲宽度以及第一和第二数据消息的长度以执行诊断检查。
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公开(公告)号：US08645020B2
公开(公告)日：2014-02-04
申请号：US13530085
申请日：2012-06-21
申请人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
发明人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
IPC分类号： G01M17/00
CPC分类号： G07C5/00 , G01P15/125 , H02M1/36 , H04L7/044
摘要： A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.
摘要翻译： 用于对从传感器发送并由接收器接收的数据消息进行诊断检查的系统包括接收机时钟计数器，预分频器计数器，校准脉冲检测器，半字节计数器和计算器。 系统接收从传感器发送的第一和第二数据消息。 第一和第二数据消息的第一和第二校准脉冲的分别为第一和第二数据消息的长度的脉冲宽度使用接收器时钟tick，预分频器和半字节计数器基于经补偿的接收机时钟信号来测量。 此后，使用计算器比较第一和第二校准脉冲的脉冲宽度以及第一和第二数据消息的长度以执行诊断检查。
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公开(公告)号：US20130312122A1
公开(公告)日：2013-11-21
申请号：US13475947
申请日：2012-05-19
申请人： Mohit Arora , Rakesh Pandey , Pushkar Sareen , Prashant Bhargava
发明人： Mohit Arora , Rakesh Pandey , Pushkar Sareen , Prashant Bhargava
IPC分类号： G06F21/02
CPC分类号： G06F21/72 , G06F21/755
摘要： A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.
摘要翻译： 篡改检测器具有用于连接到篡改检测电路的端部的输入和输出引脚和由时钟信号定时的对应的一组线性反馈移位寄存器（LFSR），用于产生作为种子值的函数的伪随机编码检测信号，以及 由反馈抽头定义的生成多项式。 比较器将从检测电路接收的信号与编码的检测信号进行比较。 复用器将选择性地从LFSR向编码的检测信号提供给输出引脚和比较器。 控制器改变伪随机编码检测信号的不同周期值的种子值。 控制器还控制生成多项式和针对伪随机编码检测信号的不同周期值的时钟信号的频率。
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