公开(公告)号：US08769247B2

公开(公告)日：2014-07-01

申请号：US13088096

申请日：2011-04-15

申请人： Michael D Estlick ,  Kevin Hurd ,  Jay Fleischman

发明人： Michael D Estlick ,  Kevin Hurd ,  Jay Fleischman

IPC分类号： G06F9/30

CPC分类号： G06F9/3855

摘要： Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.

摘要翻译： 提供了通过早期指令完成来提高处理器的效率的方法和装置。 提供了一种通过早期指令完成来提高处理器的效率的装置。 该装置包括执行单元，用于处理指令并确定稍后发出的指令是否准备好完成，或者较早发出的指令准备好完成;以及退出单元，用于在稍后的指令准备完成或退出时退出稍后发出的指令 后期指令未准备好完成的早期指令，并且较早发出的指令具有已知的良好完成状态。 提供了一种通过早期指令完成来提高处理器的效率的方法。 该方法包括当稍后发出的指令未准备好完成时，完成先前发出的指令，该指令在稍后发出的指令之前具有已知的良好完成状态。

公开(公告)号：US08819397B2

公开(公告)日：2014-08-26

申请号：US13037830

申请日：2011-03-01

申请人： Michael D. Estlick ,  Jay Fleischman ,  Debjit Das Sarma ,  Emil Talpes ,  Krishnan V. Ramani ,  Chun Liu

发明人： Michael D. Estlick ,  Jay Fleischman ,  Debjit Das Sarma ,  Emil Talpes ,  Krishnan V. Ramani ,  Chun Liu

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30094 ,  G06F9/3842

摘要： Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.

摘要翻译： 提供了通过控制字预测提高处理器效率的方法和装置。 该装置包括一个操作单元，其能够确定指令是否将第一控制字改变为第二控制字以用于处理相关指令。 执行单元使用预测的控制字处理依赖指令，并将第二控制字与预测的控制字进行比较。 当预测控制字与第二控制字不匹配时，调度单元使执行单元重新处理依赖指令。 该方法包括确定指令将第一控制字改变为第二控制字，并使用预测的控制字处理依赖指令。 将第二控制字与预测的控制字进行比较，并且当预测控制字与第二控制字不匹配时，使用第二控制字重新处理依赖指令。

公开(公告)号：US08671288B2

公开(公告)日：2014-03-11

申请号：US12974799

申请日：2010-12-21

申请人： Jay Fleischman ,  Michael Estlick ,  Kevin Hurd

发明人： Jay Fleischman ,  Michael Estlick ,  Kevin Hurd

IPC分类号： G06F1/32

CPC分类号： G06F1/329 ,  G06F1/3206 ,  G06F9/3836 ,  Y02D10/24

摘要： Methods and apparatuses are provided for controlling power consumption in a processor (or computational unit thereof). The method comprises monitoring power consumption in a processor (or computational unit) and determining that the power consumption of the processor (or computational unit) exceeds a threshold. Thereafter, instruction issuance if modified (such as by slowing or ceasing instruction issuance) within the processor (or computational unit) until the power consumption is below the threshold. The apparatus comprises a power consumption monitor for determining when power consumption within the processor exceeds a threshold. Upon that determination, a scheduler begins modify instruction issuance to one or more execution units until the power consumption is below the threshold. The modification of instruction issuance can be to slow instruction issuance or cease instruction issuance for a time period or until the power consumption is below the threshold.

摘要翻译： 提供了用于控制处理器（或其计算单元）中的功率消耗的方法和装置。 该方法包括监视处理器（或计算单元）中的功率消耗，并确定处理器（或计算单元）的功耗超过阈值。 此后，如果在处理器（或计算单元）内修改（例如通过放慢或停止指令发布）的指令发出，直到功率消耗低于阈值。 该装置包括用于确定处理器内的功率消耗何时超过阈值的功耗监视器。 在该确定时，调度器开始将指令发布修改为一个或多个执行单元，直到功耗低于阈值。 指令发布的修改可以是缓慢发出指令或停止一段时间的指令发布，或者直到功耗低于阈值。

公开(公告)号：US06374370B1

公开(公告)日：2002-04-16

申请号：US09183173

申请日：1998-10-30

申请人： John W Bockhaus ,  Jay Fleischman

发明人： John W Bockhaus ,  Jay Fleischman

IPC分类号： G06F1130

CPC分类号： G06F11/2236 ,  G11C29/16 ,  G11C29/26 ,  G11C2029/0401

摘要： A method and structure facilitates the debugging and test coverage capabilities of a microprocessor. A microprocessor having memory arrays, a debug block, and one or more built-in-self-test (BIST) engines is disclosed. The debug block is capable of driving control information out onto a state machine output bus in response to an event and the control information can be selectively used to control signature analysis or recording elements of the microprcessor, such as multiple-input-shift-registers and first-in-first-out devices, that facilitate in the monitoring and debugging of the microprocessor. The signature and recording elements may or may not be contained within the one or more BIST engines and may or may not be used in conjunction with the memory arrays or BIST engine(s) of the microprocessor.

摘要翻译： 一种方法和结构有助于微处理器的调试和测试覆盖能力。 公开了具有存储器阵列，调试块和一个或多个内置自测试（BIST）引擎的微处理器。 调试块能够响应于事件将控制信息驱动到状态机输出总线上，并且控制信息可以选择性地用于控制微处理器的签名分析或记录元件，诸如多输入移位寄存器和 先进先出的设备，便于监视和调试微处理器。 签名和记录元素可以包含在一个或多个BIST引擎中，也可以不包含在一个或多个BIST引擎中，并且可以结合使用或不与微处理器的存储器阵列或BIST引擎一起使用。

公开(公告)号：US06321320B1

公开(公告)日：2001-11-20

申请号：US09183536

申请日：1998-10-30

申请人： Jay Fleischman ,  Jeffery C Brauch ,  J. Michael Hill

发明人： Jay Fleischman ,  Jeffery C Brauch ,  J. Michael Hill

IPC分类号： G06F1700

CPC分类号： G11C29/028 ,  G11C29/16 ,  G11C2029/5002

摘要： A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

摘要翻译： 高度灵活和复杂的BIST引擎提供片上存储器阵列的高速访问，测试，表征和监控，而与其他芯片电路（如CPU内核）无关。 每个BIST引擎具有主控制块，至少一个地址生成块具有地址本地控制块和一个或多个地址数据生成块，以及至少一个具有数据本地控制块和一个或多个数据生成的数据生成块 块。 每个本地地址和数据控制块被独立编程，以分别由单独地址和数据生成块执行的操作。 主控制块又控制本地地址和数据控制块的操作，以实现对片上存储器阵列的期望的测试，访问和监视。

公开(公告)号：US06175518B1

公开(公告)日：2001-01-16

申请号：US09281612

申请日：1999-03-30

申请人： Anne P Scott ,  Jeffrey C Brauch ,  Jay Fleischman

发明人： Anne P Scott ,  Jeffrey C Brauch ,  Jay Fleischman

IPC分类号： G11C1900

CPC分类号： G11C7/103 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/28

摘要： Apparatus and method for accessing numerous remote registers on an integrated circuit chip using a minimum of interconnect traces. Plural primary nodes are configured in series along a serial data line, each of the plural primary nodes individually selectable according to a primary address presented on the serial data line. In one embodiment, a hierarchical one of the plural primary nodes includes plural secondary registers, each of the plural secondary registers individually selectable according to a secondary address presented on the serial data line. In another embodiment, a hierarchical one of the plural primary nodes includes plural secondary nodes, each of the plural secondary nodes individually selectable according to a secondary address presented on the serial data line. At least one of the plural secondary nodes includes plural tertiary registers, each of the plural tertiary registers individually selectable according to a tertiary address presented on the serial data line.

摘要翻译： 使用最少的互连轨迹访问集成电路芯片上的多个远程寄存器的装置和方法。 多个主节点沿着串行数据线串联配置，多个主节点中的每一个根据串行数据线上呈现的主地址单独地选择。 在一个实施例中，多个主节点中的分层的一个包括多个辅助寄存器，根据在串行数据线上呈现的辅助地址可以分别选择多个辅助寄存器中的每一个。 在另一个实施例中，多个主节点中的分层的一个包括多个次节点，多个次节点中的每一个根据串行数据线上呈现的辅助地址可单独选择。 多个次要节点中的至少一个包括多个三级寄存器，根据串行数据线上呈现的三级地址，可以分别选择多个三级寄存器中的每一个。

公开(公告)号：US09028067B1

公开(公告)日：2015-05-12

申请号：US14288887

申请日：2014-05-28

申请人： Jay Fleischman ,  Jerald A Bovino

发明人： Jay Fleischman ,  Jerald A Bovino

IPC分类号： A61B3/14 ,  G02C5/00 ,  A61B3/113 ,  G02C7/02

CPC分类号： A61B3/113 ,  G02B27/0093 ,  G02B27/017 ,  G02B2027/0138 ,  G02B2027/014 ,  G02B2027/0178 ,  G02B2027/0187 ,  G02C7/086 ,  G02C11/10 ,  G02C2202/10 ,  G09B21/008

摘要： A diseased retina has a blind spot where the center of the retina, called the fovea, exists. A compensation system could comprise first measuring a patient's healthy regions of the retina called PRL. A video camera could be mounted on a table, such as for reading applications, but preferably mounted on an eyeglass frame, capture an area of regard (AR). This AR is sent to a computer which directs a projector (such as a MEMS projector) to direct the AR using his healthy area of his retina. Improvements include adding an eyeball location sensor to keep the AR focused on a moving PRL. Another improvement is dithering the AR image in millimeter sized oscillations on the moving PRL. Reading enhancement software such as Spritz® can be integrated into the computer to display the enhanced text onto the PRL.

摘要翻译： 病变的视网膜有一个盲点，视网膜的中心，称为中央凹，存在。 补偿系统可以包括首先测量称为PRL的视网膜的患者的健康区域。 视频摄像机可以安装在桌子上，例如用于阅读应用，但优选地安装在眼镜架上，捕获区域（AR）。 该AR被发送到指导投影仪（例如MEMS投影仪）的计算机，以使用他的视网膜的健康区域来引导AR。 改进包括添加一个眼球位置传感器来保持AR集中在移动的PRL上。 另一个改进是在移动的PRL上以毫米大小的振荡抖动AR图像。 阅读增强软件（如Spritz®）可以集成到计算机中，以将增强的文本显示在PRL上。

公开(公告)号：US06249465B1

公开(公告)日：2001-06-19

申请号：US09506620

申请日：2000-02-18

申请人： Donald R Weiss ,  Jay Fleischman ,  Jeffery C Brauch

发明人： Donald R Weiss ,  Jay Fleischman ,  Jeffery C Brauch

IPC分类号： G11C700

CPC分类号： G11C29/802 ,  G11C29/848

摘要： A system and method are disclosed which provide the capability of repairing an optimum number of defective memory segments, such as RAM segments, in order to minimize the amount of unused repairing circuitry, such as fuses used for repairing defects within the memory. A preferred embodiment of the present invention provides a RAM block implemented such that the number of fuses required for repairing defects therein is proportional to the optimum number of defective segments capable of being repaired. A preferred embodiment allows for repairing an optimum number of defective segments, while being capable of repairing any of the segments (up to the optimum number) by mapping repair data to an appropriate defective segment. A preferred embodiment provides a repairable RAM block comprising multiple segments of RAM memory cells that are each repairable, a state machine capable of generating repair data for repairing one or more defective segments, a scan address machine capable of generating data identifying one or more defective segments, and a mapping circuitry for mapping the generated repair data of the state machine to the one or more defective segments specified by the scan address machine. Accordingly, by providing the capability of mapping generated repair data to any one of the segments of RAM that is detected as being defective, a preferred embodiment enables repairing an optimum number of defective segments, without being required to provide sufficient circuitry for repairing every segment of RAM.

摘要翻译： 公开了一种系统和方法，其提供修复最佳数量的缺陷存储器段（例如RAM段）的能力，以便最小化未使用的修复电路的量，例如用于修复存储器内的缺陷的熔丝。 本发明的优选实施例提供一种实现的RAM块，使得修复其中的缺陷所需的熔丝数量与能够被修复的缺陷段的最佳数量成比例。 优选实施例允许修复最佳数量的缺陷段，同时能够通过将修复数据映射到适当的缺陷段来修复任何段（达到最佳数目）。 优选实施例提供了一种可修复的RAM块，其包括可修复的多个RAM存储器单元段，能够产生用于修复一个或多个缺陷段的修复数据的状态机，能够产生标识一个或多个缺陷段的数据的扫描地址机 以及映射电路，用于将所生成的状态机的修复数据映射到由扫描地址机指定的一个或多个缺陷段。 因此，通过提供将生成的修复数据映射到被检测为有缺陷的RAM的任何一个片段的能力，优选实施例能够修复最佳数量的有缺陷的段，而不需要提供足够的电路来修复每个段的 随机存取存储器。

公开(公告)号：US06233669B1

公开(公告)日：2001-05-15

申请号：US09183172

申请日：1998-10-30

申请人： Anne P Scott ,  Jeffery C Brauch ,  Jay Fleischman

发明人： Anne P Scott ,  Jeffery C Brauch ,  Jay Fleischman

IPC分类号： G06F932

CPC分类号： G11C29/20 ,  G11C8/00 ,  G11C8/12

摘要： An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.

摘要翻译： 用于产生存储器阵列的地址的改进的方法和结构便于通过向被测试的存储器单元生成任何相邻存储器单元的地址来测试存储器单元。 地址生成提供向包括北，南，东，西，东北，西北，东南，西南在内的任何方向移动到任何相邻的存储单元。 可以通过锻炼可编程初始化特征来选择性地生成任何存储器单元的地址，甚至非相邻存储器单元的地址。

公开(公告)号：US06298429B1

公开(公告)日：2001-10-02

申请号：US09660032

申请日：2000-09-12

申请人： Anne P. Scott ,  Jeffery C Brauch ,  Jay Fleischman

发明人： Anne P. Scott ,  Jeffery C Brauch ,  Jay Fleischman

IPC分类号： G06F1206

CPC分类号： G11C29/20 ,  G11C8/00 ,  G11C8/12

摘要： An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by defining a current memory address, choosing one or more modes by which increment-generated, decrement-generated, or combination increment/decrement addresses that define a next memory address are generated, and generating the row address and the column address of the next memory address in accordance with interdependent row carry-out and column carry-out operations.

摘要翻译： 用于产生存储器阵列的地址的改进的方法和结构便于通过向被测试的存储器单元生成任何相邻存储器单元的地址来测试存储器单元。 地址生成提供向包括北，南，东，西，东北，西北，东南，西南在内的任何方向移动到任何相邻的存储单元。 可以通过定义当前存储器地址来选择性地生成任何存储器单元的地址，甚至非相邻存储器单元的地址，选择一个或多个模式，通过该模式增量生成，减量生成或组合递增/递减地址 生成定义下一个存储器地址，并且根据相互依赖的行执行和列执行操作产生下一个存储器地址的行地址和列地址。