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1.发明申请Detecting Data Transmission Errors In An Inter-Integrated Circuit ('I2C') System 有权检测内部集成电路（“I2C”）系统中的数据传输错误公开(公告)号：US20130346835A1
公开(公告)日：2013-12-26
申请号：US13530318
申请日：2012-06-22
CPC分类号： H03M13/098 , H04L2001/0094
摘要： Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.
摘要翻译： 检测I2C系统中的数据传输错误，该系统包括源设备，目标设备和耦合I2C源设备和目标设备的信号线，包括：由I2C源设备从I2C源设备接收数据传输信号， 数据传输信号用一组位编码; 通过I2C目的地设备检测位组中的预选位的上升时间; 如果检测到的上升时间小于预定阈值，则确定I2C源设备在信号中注入了奇偶校验位，并且如果检测到的上升时间不小于预定阈值，则确定I2C源设备未注入 信号中的奇偶校验位; 以及确定所述数据传输信号是否包括与所述位组的奇偶校验有关的错误。
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2.发明申请公开(公告)号：US20130343197A1
公开(公告)日：2013-12-26
申请号：US13530245
申请日：2012-06-22
IPC分类号： H04L12/26
CPC分类号： G06F13/4291
摘要： Operating a demultiplexer on an I2C bus, the demultiplexer including a set of input signal lines from an I2C master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the I2C master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.
摘要翻译： 在I2C总线上操作解复用器，解复用器包括来自I2C主机和多组输出信号线的一组输入信号线，该多路分配器被配置为根据解复用器选择信号线在输出之间耦合输入 将解复用器耦合到上升时间检测电路，其中上升时间检测电路还耦合到输入信号线和上升时间检测电路：监视至少一个输入信号线的电压，包括：从 I2C主机，其中一条信号; 并检测信号的上升时间; 并且如果信号的上升时间小于预定阈值，则配置解复用器以改变输入信号线与第一组输出到第二组的耦合。
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3.发明授权Dynamically optimizing bus frequency of an inter-integrated circuit (‘I2C’) bus 有权动态优化集成电路（“I2C”）总线的总线频率公开(公告)号：US08959380B2
公开(公告)日：2015-02-17
申请号：US13467332
申请日：2012-05-09
IPC分类号： G06F1/08
CPC分类号： G06F1/324 , G06F9/44 , G06F13/38 , G06F13/4282
摘要： Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.
摘要翻译： 优化I2C总线频率，总线包括耦合主节点和从节点的信号线，耦合到上升时间检测电路的信号线监视信号线的电压，电压在逻辑低电平和逻辑高电平之间交替，其中优化 频率包括：在信号线上升期间检测第一电压，第一电压大于逻辑低电压; 启动一个计数器，为电路的每个时钟周期增加一次; 检测信号线上的第二电压，第二电压大于第一电压并小于逻辑高电平; 停止柜台 根据时钟周期和计数器值计算上升时间; 确定上升时间是否大于最大阈值; 并且如果计算的上升时间大于最大阈值，则增加I2C总线频率。
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4.发明授权公开(公告)号：US08954634B2
公开(公告)日：2015-02-10
申请号：US13530245
申请日：2012-06-22
IPC分类号： G06F3/00
CPC分类号： G06F13/4291
摘要： Operating a demultiplexer on an I2C bus, the demultiplexer including a set of input signal lines from an I2C master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the I2C master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.
摘要翻译： 在I2C总线上操作解复用器，解复用器包括来自I2C主机和多组输出信号线的一组输入信号线，该多路分配器被配置为根据解复用器选择信号线在输出之间耦合输入 将解复用器耦合到上升时间检测电路，其中上升时间检测电路还耦合到输入信号线和上升时间检测电路：监视至少一个输入信号线的电压，包括：从 I2C主机，其中一条信号; 并检测信号的上升时间; 并且如果信号的上升时间小于预定阈值，则配置解复用器以改变输入信号线与第一组输出到第二组的耦合。
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5.发明授权Detecting data transmission errors in an inter-integrated circuit (‘I2C’) system 有权检测集成电路（“I2C”）系统中的数据传输错误公开(公告)号：US08832538B2
公开(公告)日：2014-09-09
申请号：US13530318
申请日：2012-06-22
CPC分类号： H03M13/098 , H04L2001/0094
摘要： Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.
摘要翻译： 检测I2C系统中的数据传输错误，该系统包括源设备，目标设备和耦合I2C源设备和目标设备的信号线，包括：由I2C源设备从I2C源设备接收数据传输信号， 数据传输信号用一组位编码; 通过I2C目的地设备检测位组中的预选位的上升时间; 如果检测到的上升时间小于预定阈值，则确定I2C源设备在信号中注入了奇偶校验位，并且如果检测到的上升时间不小于预定阈值，则确定I2C源设备未注入 信号中的奇偶校验位; 以及确定所述数据传输信号是否包括与所述位组的奇偶校验有关的错误。
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6.发明授权Chip select (‘CS’) multiplication in a serial peripheral interface (‘SPI’) system 有权串行外设接口（“SPI”）系统中的片选（'CS'）相乘公开(公告)号：US09015394B2
公开(公告)日：2015-04-21
申请号：US13530284
申请日：2012-06-22
CPC分类号： G06F13/4291 , G06F1/3215 , G06F11/349 , G06F13/4282 , H03M1/34
摘要： Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.
摘要翻译： 包括SPI主机，CS乘法器，多个SPI从机以及下降时间检测电路的SPI系统中的片选（'CS'）相乘，其中SPI主机耦合到CS乘法器和下降时间检测 CS乘法器包括多个CS输出，每个CS输出耦合到SPI从机，CS乘法包括：从SPI主机接收CS信号线上的CS信号; 检测CS信号的下降时间; 并且如果CS信号的下降时间小于预定阈值，则由下降时间检测电路配置CS乘法器，以便在第一CS输出上提供CS信号以在第二CS输出上提供CS信号 CS输出。
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7.发明申请Chip Select ('CS') Multiplication In A Serial Peripheral Interface ('SPI') System 有权串行外设接口（“SPI”）系统中的片选（'CS'）乘法公开(公告)号：US20130346658A1
公开(公告)日：2013-12-26
申请号：US13530284
申请日：2012-06-22
IPC分类号： G06F13/40
CPC分类号： G06F13/4291 , G06F1/3215 , G06F11/349 , G06F13/4282 , H03M1/34
摘要： Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.
摘要翻译： 包括SPI主机，CS乘法器，多个SPI从机以及下降时间检测电路的SPI系统中的片选（'CS'）相乘，其中SPI主机耦合到CS乘法器和下降时间检测 CS乘法器包括多个CS输出，每个CS输出耦合到SPI从机，CS乘法包括：从SPI主机接收CS信号线上的CS信号; 检测CS信号的下降时间; 并且如果CS信号的下降时间小于预定阈值，则由下降时间检测电路配置CS乘法器，以便在第一CS输出上提供CS信号以在第二CS输出上提供CS信号 CS输出。
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公开(公告)号：US20140013151A1
公开(公告)日：2014-01-09
申请号：US13541750
申请日：2012-07-04
CPC分类号： G06F13/4282
摘要： In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.
摘要翻译： 根据本发明的一个实施例，可以提供用于I2C总线接口的I2C总线复用电路。 I2C总线复用电路可以通过I2C总线从I2C主器件检测启动命令，缓冲来自I2C主器件的数据，检测总线串行时钟（SCL）线的时钟频率，从而有助于I2C总线接口中的多路开关切换 的I2C主器件，将I2C主器件的串行数据（SDA）线保持在时钟拉伸状态，并根据检测到的I2C主器件SCL的时钟频率选择一个端口。 该方法还可以包括将所缓冲的数据发送到所选端口上的I2C从设备。 该方法还可以包括从所选端口上的I2C从设备接收确认。
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公开(公告)号：US20140071647A1
公开(公告)日：2014-03-13
申请号：US13610923
申请日：2012-09-12
IPC分类号： H05K7/00
CPC分类号： H05K7/1429 , H01L23/40 , H01L23/4006 , H01L2023/4056 , H01L2023/4068 , H01L2023/4087 , H01L2924/0002 , H05K7/1007 , H01L2924/00
摘要： A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.
摘要翻译： 计算机处理器保持装置包括负载框架，负载板和一对可缩回盖构件。 负载框架可以固定到处理器安装位置周围的电路板。 负载板枢转地联接到负载框架，并且可在打开状态之间枢转，以在处理器安装位置处接收处理器并且与接收到的处理器的外围封闭。 当负载板关闭时，负载板具有对处理器安装位置开放的窗口。 可缩回的盖构件跨越窗户，并且可沿轨道彼此交替移动以覆盖处理器安装位置并远离彼此以暴露处理器安装位置。
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公开(公告)号：US08902611B2
公开(公告)日：2014-12-02
申请号：US13610923
申请日：2012-09-12
IPC分类号： H05K7/02
CPC分类号： H05K7/1429 , H01L23/40 , H01L23/4006 , H01L2023/4056 , H01L2023/4068 , H01L2023/4087 , H01L2924/0002 , H05K7/1007 , H01L2924/00
摘要： A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.
摘要翻译： 计算机处理器保持装置包括负载框架，负载板和一对可缩回盖构件。 负载框架可以固定到处理器安装位置周围的电路板。 负载板枢转地联接到负载框架，并且可在打开状态之间枢转，以在处理器安装位置处接收处理器并且与接收到的处理器的外围封闭。 当负载板关闭时，负载板具有对处理器安装位置开放的窗口。 可缩回的盖构件跨越窗户，并且可沿轨道彼此交替移动以覆盖处理器安装位置并远离彼此以暴露处理器安装位置。
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