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1.发明授权Method and apparatus for scan testing an array in a data processing system 失效用于在数据处理系统中扫描测试阵列的方法和装置
公开(公告)号：US5414714A
公开(公告)日：1995-05-09
申请号：US857878
申请日：1992-03-26
IPC分类号： G01R31/317 , G11C29/32 , G01R31/28 , G06F11/00
CPC分类号： G01R31/317 , G11C29/32
摘要： A method and apparatus for scan testing an array (20) in a data processing system (10). In one form, the present invention uses a scanning sense amplifier (22x) which can perform the three functions of a sense amplifier, a master test latch for scan testing, and a slave test latch for scan testing. Using one scanning sense amplifier (22x) to perform all three functions reduces the amount of circuitry required to scan test an array (20). The same stimulus is applied twice to the array (20); and half of the output data bits are scanned out during each application of the stimulus. One extra output data bit is also scanned out during each application of the stimulus. The end result is a reduction in the circuitry required to perform scan testing.
摘要翻译： 一种用于扫描测试数据处理系统（10）中的阵列（20）的方法和装置。 在一种形式中，本发明使用可执行读出放大器，用于扫描测试的主测试锁存器和用于扫描测试的从测试锁存器的三个功能的扫描读出放大器（22x）。 使用一个扫描读出放大器（22x）执行所有三个功能可以减少扫描测试阵列（20）所需的电路数量。 对阵列（20）施加相同的刺激两次; 并且在每次应用刺激期间扫描输出数据位的一半。 每次应用刺激时，也会扫描一个额外的输出数据位。 最终的结果是减少执行扫描测试所需的电路。
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2.发明授权Microprogrammed data processor which includes a microsequencer in which a next microaddress output of a microROM is connected to the or-plane of an entry PLA 失效微编程数据处理器，其包括微定序器，其中微ROM的下一微地址输出连接到条目PLA的平面
公开(公告)号：US5412785A
公开(公告)日：1995-05-02
申请号：US38046
申请日：1993-03-26
IPC分类号： G06F9/26
CPC分类号： G06F9/265
摘要： A data processor microsequencer having a non-multiplexed internal address bus is provided. The microsequencer includes a nanoROM, for providing control information to an execution unit, an entry point PLA for decoding a macroinstruction address and providing an initial microinstruction address, and a microROM, for providing the next microinstruction address during instruction sequencing. The entry PLA accesses macroinstructions from an instruction pipeline, and decodes the macroinstructions, thereby providing an initial microinstruction address for the microroutine to perform the macroinstruction. The initial microinstruction address is temporarily stored in a microprogram counter latch (uPC) and provided to the microROM or the nanoROM for decoding. The microROM decodes the initial microinstruction address and provides N output bits which are routed directly into the PLA, and subsequently provided to the uPC. The uPC selectively transfers the next microaddress to the microROM, and the microROM decodes the next microaddress, thereby providing subsequent microaddresses in the microroutine directly to the PLA. Strobe circuitry selectively activates either the microROM and the PLA, and in so doing, determines which unit provides the microaddress to the uPC.
摘要翻译： 提供具有非复用内部地址总线的数据处理器微定序器。 微定序器包括用于向执行单元提供控制信息的纳米ROM，用于解码宏指令地址并提供初始微指令地址的入口点PLA和用于在指令排序期间提供下一微指令地址的微ROM。 条目PLA从指令流水线访问宏指令，并解码宏指令，从而为微程序提供初始微指令地址以执行宏指令。 初始微指令地址临时存储在微程序计数器锁存器（uPC）中，并提供给微ROM或nanoROM进行解码。 微ROM解码初始微指令地址，并提供N个输出位，它们直接路由到PLA中，随后提供给uPC。 uPC选择性地将下一个微地址传送到微ROM，并且microROM对下一个微地址进行解码，从而将微阵列中的后续微地址直接提供给PLA。 选通电路选择性地激活微ROM和PLA，并且这样做确定哪个单元向uPC提供微地址。
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3.发明授权Data processing system for performing a shifting operation and a constant generation operation and method therefor 失效用于执行换档操作的数据处理系统和恒定生成操作及其方法
公开(公告)号：US5301345A
公开(公告)日：1994-04-05
申请号：US695161
申请日：1991-05-03
摘要： A data processing system (10) has a control selector (30) which has at least one conductor used for the common functions of shifting data and controling the generation of constants in an execution unit (26). A logic circuit (34) provides control signals to enable the control selector (30) to perform an information transfer, a shift operation, or a constant generation function. A plurality of constant signals enables a plurality of transistors (82, 114, 130, 84, 132, 86, 134) to generate a plurality of constant values. During an operation to shift data, a portion of the logic circuit (30) which generates a constant value is disabled by a Shift Disable signal. The conductors used to enable the control electrodes of the transistors during a constant generation function are used to shift data a predetermined number of bits when two shift signals are asserted.
摘要翻译： 数据处理系统（10）具有控制选择器（30），该控制选择器具有至少一个导体，用于在执行单元（26）中移动数据和控制常数的产生的共同功能。 逻辑电路（34）提供控制信号以使得控制选择器（30）能够执行信息传送，移位操作或恒定生成功能。 多个恒定信号使多个晶体管（82,114,130,84,132,86,134）能够产生多个恒定值。 在移位数据的操作期间，通过移位禁止信号禁止产生常数值的逻辑电路（30）的一部分。 用于在恒定生成功能期间使晶体管的控制电极能够使用的导体用于当两个移位信号被断言时将数据移位预定数量的位。
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公开(公告)号：US5410725A
公开(公告)日：1995-04-25
申请号：US37744
申请日：1993-03-26
摘要： A data processor has a microcode memory which is reduced in size by sharing word locations having the same contents. When one of the shared word locations is addressed, a control signal is generated and coupled to a select circuit. The select circuit outputs a predetermined operand in place of the contents of the addressed shared word location which can contain a "do not care" operand value. Selective sharing or combining of the word locations is utilized when structuring the memory to optimize savings in circuit area.
摘要翻译： 数据处理器具有通过共享具有相同内容的字位置来减小大小的微代码存储器。 当寻址一个共享字位置时，产生控制信号并耦合到选择电路。 选择电路输出预定的操作数，代替可以包含“不关心”操作数值的寻址共享字位置的内容。 当构建存储器以优化电路区域的节省时，利用单词位置的选择性共享或组合。
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5.发明授权Data processor having a multi-stage instruction pipe and selection logic responsive to an instruction decoder for selecting one stage of the instruction pipe 失效具有多级指令管道的数据处理器和响应于用于选择指令管道的一级的指令解码器的选择逻辑
公开(公告)号：US5276824A
公开(公告)日：1994-01-04
申请号：US79429
申请日：1993-06-21
CPC分类号： G06F9/3822 , G06F1/32 , G06F9/265 , G06F9/30145
摘要： A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.
摘要翻译： 具有降低功耗的微定序器的数据处理器选择性地激活指令解码单元和微代码序列控制存储器单元。 微定序器具有用多个PLA实现的指令解码单元，并且还具有用于提供下一个微地址的微编码ROM。 指令解码单元输出下一个微地址，下一个PLA字段和一个ROM-or-PLA控制位。 控制位用于最小化数据处理器的功耗。 当需要下一条指令解码来激活预定的解码单元时，下一个PLA字段被锁存并用于选择单个解码单元。 可以在数据处理器中执行早期宏指令分支，从而提高性能。
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6.发明授权Data processor microsequencer having multiple microaddress sources and next microaddress source selection 失效数据处理器微定序器具有多个微地址源和下一个微地址源选择
公开(公告)号：US5241637A
公开(公告)日：1993-08-31
申请号：US15388
申请日：1993-02-08
IPC分类号： G06F9/26
摘要： A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.
摘要翻译： 具有降低功耗的微定序器的数据处理器选择性地激活指令解码单元和微代码序列控制存储器单元。 微定序器具有用多个PLA实现的指令解码单元，并且还具有用于提供下一个微地址的微编码ROM。 指令解码单元输出下一个微地址，下一个PLA字段和一个ROM-or-PLA控制位。 控制位用于最小化数据处理器的功耗。 当需要下一条指令解码来激活预定的解码单元时，下一个PLA字段被锁存并用于选择单个解码单元。 可以在数据处理器中执行早期宏指令分支，从而提高性能。
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