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17 条记录 (耗时 0.025 秒)

    Voltage detecting circuit
    1.
    发明授权
    Voltage detecting circuit 失效
    电压检测电路

    公开(公告)号：US4521696A

    公开(公告)日：1985-06-04

    申请号：US395424

    申请日：1982-07-06

    申请人： Kuppuswamy Raghunathan

    发明人： Kuppuswamy Raghunathan

    IPC分类号： H03K19/0948 ,  H03K5/153 ,  H03K5/24

    CPC分类号： H03K19/0948

    摘要： A voltage detecting circuit is disclosed having a first field effect transistor of a first type coupled in series with a second field effect transistor of a second type between a first supply voltage node and an input node, with the current channel regions coupled to the same node as the sources thereof, and the gates thereof coupled to a second supply voltage node. If the on resistance of the second transistor is significantly greater than that of the first transistor, the output node, formed by the common drains of the transistors, will be substantially the first supply voltage when the input signal is absent, and the voltage of the input signal signal when the latter is present.

    摘要翻译： 公开了一种电压检测电路，其具有第一类型的第一场效应晶体管，其与第一电源电压节点和输入节点之间的第二类型的第二场效应晶体管串联耦合，其中当前沟道区域耦合到同一节点 作为其来源，其栅极耦合到第二电源电压节点。 如果第二晶体管的导通电阻显着大于第一晶体管的导通电阻，则由晶体管的公共漏极形成的输出节点将在输入信号不存在时基本上是第一电源电压， 输入信号信号。

    High voltage decoder
    3.
    发明授权
    High voltage decoder 失效
    高压解码器

    公开(公告)号：US4689504A

    公开(公告)日：1987-08-25

    申请号：US811227

    申请日：1985-12-20

    申请人： Kuppuswamy Raghunathan ,  Jeffrey R. Jorvig ,  Stephen L. Smith

    发明人： Kuppuswamy Raghunathan ,  Jeffrey R. Jorvig ,  Stephen L. Smith

    IPC分类号： G11C16/12 ,  H03K3/356 ,  H03K17/687 ,  H03K19/092

    CPC分类号： G11C16/12 ,  H03K3/356104

    摘要： A high voltage CMOS decoder and level translator for use in conjunction with EPROMS and EEPROMS utilizes additional series coupled field effect transistors maintained in an on condition so a to prevent the voltage across the pull-up and pull-down field effect transistors from exceeding their break down voltages. For example, in addition to a pull-up P-channel field effect transistor and a pull-down N-channel field effect transistor in the output inverter circuit, additional P-channel and N-channel field effect transistors are coupled in series between the pull-up and pull-down transistors to maintain the voltage across the pull-up and pull-down transistors from exceeding there breakdown voltages.

    摘要翻译： 与EPROMS和EEPROMS一起使用的高电压CMOS解码器和电平转换器利用保持在导通条件下的附加串联耦合场效应晶体管，以防止上拉和下拉场效应晶体管两端的电压超过其断点 降压。 例如，除了输出反相器电路中的上拉P沟道场效应晶体管和下拉N沟道场效应晶体管之外，附加的P沟道和N沟道场效应晶体管串联耦合在 上拉和下拉晶体管，以保持上拉和下拉晶体管两端的电压超过击穿电压。

    Data processor with microcode memory compression
    5.
    发明授权
    Data processor with microcode memory compression 失效
    数据处理器采用微码存储器压缩

    公开(公告)号：US5410725A

    公开(公告)日：1995-04-25

    申请号：US37744

    申请日：1993-03-26

    申请人： Robert J. Skruhak ,  James C. Nash ,  Kuppuswamy Raghunathan

    发明人： Robert J. Skruhak ,  James C. Nash ,  Kuppuswamy Raghunathan

    IPC分类号： G06F9/22 ,  G06F9/26

    CPC分类号： G06F9/26 ,  G06F9/223

    摘要： A data processor has a microcode memory which is reduced in size by sharing word locations having the same contents. When one of the shared word locations is addressed, a control signal is generated and coupled to a select circuit. The select circuit outputs a predetermined operand in place of the contents of the addressed shared word location which can contain a "do not care" operand value. Selective sharing or combining of the word locations is utilized when structuring the memory to optimize savings in circuit area.

    摘要翻译： 数据处理器具有通过共享具有相同内容的字位置来减小大小的微代码存储器。 当寻址一个共享字位置时，产生控制信号并耦合到选择电路。 选择电路输出预定的操作数，代替可以包含“不关心”操作数值的寻址共享字位置的内容。 当构建存储器以优化电路区域的节省时，利用单词位置的选择性共享或组合。

    Data transfer between integrated circuit timer channels
    6.
    发明授权
    Data transfer between integrated circuit timer channels 失效
    集成电路定时器通道之间的数据传输

    公开(公告)号：US5721889A

    公开(公告)日：1998-02-24

    申请号：US555963

    申请日：1995-11-13

    申请人： Gary Lynn Miller ,  Kuppuswamy Raghunathan ,  Timothy Ernest Litch ,  Marcella Evelyn Meyer

    发明人： Gary Lynn Miller ,  Kuppuswamy Raghunathan ,  Timothy Ernest Litch ,  Marcella Evelyn Meyer

    IPC分类号： G06F1/08 ,  G06F13/16 ,  G06F1/04

    CPC分类号： G06F1/08 ,  G06F13/1689

    摘要： Referring to FIGS. 20-24, in one embodiment, data can be transferred from the data register of a top adjacent timer channel (e.g. 400 in FIG. 20) to the data register of the timer channel itself (401), and from the data register of the timer channel itself (401) to the data register of the bottom adjacent timer channel (402). By programming control register bits (e.g. DVB bits 425-426, DTC bits 423-424, and DTS bits 427-428 in FIG. 21) of selected timer channels (401) to perform these inter-channel data transfers, both stacks and FIFO structures can be formed and used. Stack and FIFO data storage structures can reduce the frequency of service required by the timer channels (400-402), and thus reduce the number of interrupts which must be responded to by a CPU (13 in FIG. 1).

    摘要翻译： 参见图 如图20-24所示，在一个实施例中，数据可以从顶部相邻的定时器通道（例如图20中的400）的数据寄存器传送到定时器通道本身（401）的数据寄存器，并且从数据寄存器 定时器通道本身（401）连接到底部相邻定时器通道（402）的数据寄存器。 通过编程所选择的定时器通道（401）的控制寄存器位（例如，图21中的DVB位425-426，DTC位423-424和DTS位427-428）来执行这些信道间数据传输，堆栈和FIFO 可以形成和使用结构。 堆栈和FIFO数据存储结构可以减少定时器通道（400-402）所需的服务频率，从而减少CPU（图1中的13）必须响应的中断次数。

    Erase circuit for CMOS EEPROM
    9.
    发明授权
    Erase circuit for CMOS EEPROM 失效
    擦除CMOS EEPROM的电路

    公开(公告)号：US4751678A

    公开(公告)日：1988-06-14

    申请号：US797273

    申请日：1985-11-12

    申请人： Kuppuswamy Raghunathan

    发明人： Kuppuswamy Raghunathan

    IPC分类号： G11C16/14 ,  G11C7/00

    CPC分类号： G11C16/14

    摘要： An erase circuit for an EEPROM is provided which only uses enhancement type transistors. This eliminates having to use additional processing steps to provide depletion type transistors in a CMOS process. Enhancement type transistors are used to provide the erase voltage to the control gate of an electrically erasable memory cell. An additional enhancement type transistor is used to maintain the control gate in a non-floating condition during non-erase periods.

    摘要翻译： 提供了仅用于增强型晶体管的EEPROM的擦除电路。 这消除了不必在CMOS工艺中使用额外的处理步骤来提供耗尽型晶体管。 增强型晶体管用于向电可擦除存储单元的控制栅极提供擦除电压。 在非擦除期间，使用附加的增强型晶体管来将控制栅极保持在非浮置状态。

    Apparatus for reducing power consumed by a static microprocessor
    10.
    发明授权
    Apparatus for reducing power consumed by a static microprocessor 失效
    用于降低静态微处理器消耗功率的装置

    公开(公告)号：US4748559A

    公开(公告)日：1988-05-31

    申请号：US65293

    申请日：1979-08-09

    申请人： Philip S. Smith ,  Kuppuswamy Raghunathan

    发明人： Philip S. Smith ,  Kuppuswamy Raghunathan

    IPC分类号： G06F1/32 ,  G06F1/04

    CPC分类号： G06F9/30083 ,  G06F1/3228

    摘要： In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.

    摘要翻译： 响应于软件指令，通过禁止产生时钟脉冲，将静态微处理器置于低电流模式。 提供了当STOP指令被解码时禁用主振荡器的装置。 提供了在WAIT指令被解码而禁用主振荡器时抑制时钟脉冲的附加装置。 接收到复位或中断信号后，再次使能时钟脉冲生成。