-
公开(公告)号：US20060133366A1
公开(公告)日：2006-06-22
申请号：US11016197
申请日：2004-12-17
申请人： Michael Ho , Miriam Qunell , Jean-Michel Caia
发明人： Michael Ho , Miriam Qunell , Jean-Michel Caia
CPC分类号： H04L49/10 , H04J3/1611
摘要： A method and system for interconnecting multiple distributed components in a communication network is provided. The design includes a multiple order cross connection fabric employed to interconnect multiple orders of data with at least one distributed component in the communication network. The design may further include at least one order of path termination and adaptation connection, where the at least one order of path termination and adaptation connection providing an interface between the multiple order cross connection fabric and a data management system. The design may be implemented in a SONET/SDH environment.
-
公开(公告)号：US20060067314A1
公开(公告)日：2006-03-30
申请号：US10954947
申请日：2004-09-29
申请人： Michael Ho , Miriam Qunell , Jeff Fedders , Jean-Michel Caia
发明人： Michael Ho , Miriam Qunell , Jeff Fedders , Jean-Michel Caia
CPC分类号： H04J3/1611 , H04J2203/0025 , H04J2203/0057 , H04J2203/0066
摘要： Techniques to allocate overhead processing and overhead generation among at least data and overhead processors. The data processor and overhead processor may be provided in separate integrated circuits. The data processor and overhead processor may be provided in separate line cards. Multiple data processors may share use of one or more overhead processors. Payload portions of standardized frames may be used to transfer overhead between the data and overhead processors.
摘要翻译： 在至少数据和开销处理器之间分配开销处理和开销生成的技术。 数据处理器和开销处理器可以在单独的集成电路中提供。 可以在单独的线路卡中提供数据处理器和开销处理器。 多个数据处理器可以共享一个或多个开销处理器的使用。 标准化帧的有效载荷部分可用于在数据和开销处理器之间传送开销。
-
公开(公告)号：USRE45248E1
公开(公告)日：2014-11-18
申请号：US13273182
申请日：2011-10-13
申请人： Michael Ho , Miriam Qunell , Jean-Michel Caia
发明人： Michael Ho , Miriam Qunell , Jean-Michel Caia
CPC分类号： H04L49/10 , H04J3/1611
摘要： A method and system for interconnecting multiple distributed components in a communication network is provided. The design includes a multiple order cross connection fabric employed to interconnect multiple orders of data with at least one distributed component in the communication network. The design may further include at least one order of path termination and adaptation connection, where the at least one order of path termination and adaptation connection providing an interface between the multiple order cross connection fabric and a data management system. The design may be implemented in a SONET/SDH environment.
摘要翻译： 提供了一种用于互连通信网络中的多个分布式组件的方法和系统。 该设计包括用于将多个数据顺序与通信网络中的至少一个分布式组件互连的多阶交叉连接结构。 该设计可以进一步包括路径终止和适配连接的至少一个顺序，其中路径终止和自适应连接的至少一个顺序提供多级交叉连接结构和数据管理系统之间的接口。 该设计可以在SONET / SDH环境中实现。
-
公开(公告)号：US20070086479A1
公开(公告)日：2007-04-19
申请号：US11359819
申请日：2006-02-21
IPC分类号： H04L12/66
CPC分类号： H04L49/9073 , H04L49/90
摘要： Techniques are described herein that may be used to buffer traffic received at a communications device. For example, a buffer external from a traffic processor may be used to buffer traffic in ingress or egress directions. For example, a bandwidth in each of directions of to and from the buffer may be less than a sum of maximum bandwidths in ingress and egress directions. For example, a single memory interface may be used to communicatively couple the buffer and the traffic processor.
摘要翻译： 本文描述了可用于缓冲在通信设备处接收的业务的技术。 例如，可以使用来自业务处理器的外部缓冲器来缓冲入口或出口方向上的流量。 例如，往返缓冲器的每个方向上的带宽可以小于入口和出口方向上的最大带宽之和。 例如，可以使用单个存储器接口来通信地耦合缓冲器和流量处理器。
-
公开(公告)号：US07061867B2
公开(公告)日：2006-06-13
申请号：US10115229
申请日：2002-04-02
CPC分类号： H04L47/6215 , H04L47/10 , H04L47/39 , H04L47/50 , H04L47/521 , H04L47/627
摘要： The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.
-
公开(公告)号：US20120269511A1
公开(公告)日：2012-10-25
申请号：US13091908
申请日：2011-04-21
IPC分类号： H04J14/00
CPC分类号： H04J3/1664 , H04J2203/0089
摘要： Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.
摘要翻译： 信号格式转换装置和方法包括在与第一参考时钟速率相关联的第一信号格式和不同于第一信号格式的第二信号格式之间转换数据信号，并且与不同于第一参考时钟的第二参考时钟速率相关联 率。 通过控制在第一信号格式和第二信号格式之间转换数据信号中应用的同步的第二参考时钟速率来改变第二信号格式的周期以匹配第三信号格式的周期。 同步的第二参考时钟速率与第二参考时钟速率不同，并且与第三参考时钟速率同步。 第三参考时钟速率与第三信号格式相关联。 这种同步简化了第二和第三信号格式之间信号的转换。
-
7.发明授权公开(公告)号：US07583599B1
公开(公告)日：2009-09-01
申请号：US10952241
申请日：2004-09-27
申请人： Jing Ling , Vasan Karighattam , Jean-Michel Caia , Edward Pullin , Mark Feuerstraeter , Juan-Carlos Calderon
发明人： Jing Ling , Vasan Karighattam , Jean-Michel Caia , Edward Pullin , Mark Feuerstraeter , Juan-Carlos Calderon
IPC分类号： G01R31/08
CPC分类号： H04J3/1617 , H04J2203/0082 , Y10S370/907
摘要： A method and apparatus for transferring data traffic, such as in a SONET/SDH environment, is provided. Two designs are presented, each utilizing a dual device design, where one device performs GFP Framing and the other device performs GFP-T adaptation. The method and apparatus include a first device having a first device FIFO, the first device configured to receive data and assemble data into packets and transfer data across a packet interface when the first device FIFO contains more than N bytes. A second device comprises a second device FIFO, the second device configured to receive data packets from the packet interface and utilize a plurality of thresholds to maintain a quantity of data in the second device FIFO within a predetermined range. Depending on the design employed, control codes, such as 65B_PAD control codes, may be added in the first device under certain conditions to facilitate data transfer.
摘要翻译： 提供了一种用于传送数据业务的方法和装置，例如在SONET / SDH环境中。 呈现了两种设计，每种都使用双重设备设计，其中一个设备执行GFP帧，另一个设备执行GFP-T适配。 所述方法和装置包括具有第一设备FIFO的第一设备，所述第一设备被配置为当所述第一设备FIFO包含多于N个字节时，接收数据并将数据组合成分组并且在分组接口上传送数据。 第二设备包括第二设备FIFO，第二设备被配置为从分组接口接收数据分组，并利用多个阈值将第二设备FIFO中的数据量维持在预定范围内。 根据所采用的设计，可以在特定条件下在第一设备中添加诸如65B_PAD控制码的控制代码以便于数据传送。
-
8.发明授权Method and apparatus differential delay compensation processing of virtually concatenated data 有权虚拟级联数据的方法和装置差分延迟补偿处理公开(公告)号：US07508830B1
公开(公告)日：2009-03-24
申请号：US10927833
申请日：2004-08-27
IPC分类号： H04L12/56
CPC分类号： H04J3/0632
摘要： A method and apparatus for determining a read address for received data in a communications network employing virtually concatenated payloads is provided. The method and apparatus comprise determining a minimum write address using a plurality of memory elements and using the minimum write address in connection with received read addresses to determine group read addresses.
摘要翻译： 提供了一种用于在采用虚拟级联有效载荷的通信网络中确定接收数据的读取地址的方法和装置。 所述方法和装置包括使用多个存储器元件确定最小写入地址并且使用与所接收的读取地址相关联的最小写入地址来确定组读取地址。
-
9.发明授权公开(公告)号：US07460545B1
公开(公告)日：2008-12-02
申请号：US10867199
申请日：2004-06-14
申请人： Juan-Carlos Calderon , Soowan Suh , Jing Ling , Jean-Michel Caia , Augusto Alcantara , Alejandro Lenero Beracoechea
发明人： Juan-Carlos Calderon , Soowan Suh , Jing Ling , Jean-Michel Caia , Augusto Alcantara , Alejandro Lenero Beracoechea
IPC分类号： H04L12/28
CPC分类号： H04J3/062 , H04J3/047 , H04J2203/0094
摘要： A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.
摘要翻译： 提供一种用于管理用于时分复用的高速数据业务的存储器的方法和装置。 该方法和装置利用与诸如SDRAM之类的多个存储体相关联的交织方法来执行高效的数据读写。 该设计向第一存储体发出第一命令或访问命令，例如读取命令或写入命令，随后向第二存储体发送有效命令，使得能够在诸如SONET的多数据流环境中进行有效的读取和写入 / SDH虚级联环境采用差分延迟补偿。
-
10.发明授权System and method for accounting for time that a packet spends in transit through a transparent clock 有权用于计算数据包通过透明时钟传输的时间的系统和方法公开(公告)号：US09252903B2
公开(公告)日：2016-02-02
申请号：US13279043
申请日：2011-10-21
CPC分类号： H04J3/0667 , H04J3/0673 , H04L43/0852 , H04L43/106
摘要： Despite a recent revision, IEEE 1588™-2008 does not provide a complete implementation for PTP (precision time protocol) that accounts for variable delays introduced by network components. According to a broad aspect, the present disclosure provides implementations that account for variable delays introduced by network components. Therefore, the amount of time that a packet spends in transit through a transparent clock can be accounted for. According to another broad aspect, there is provided a master-slave mode that allows a transparent clock to function as a master or a slave to another clock.
摘要翻译： 尽管最近进行了修订，但IEEE 1588™-2008并没有为PTP（精确时间协议）提供一个完整的实现，可以解决由网络组件引入的可变延迟。 根据广泛的方面，本公开提供了解决由网络组件引入的可变延迟的实现。 因此，可以考虑数据包通过透明时钟传输的时间量。 根据另一个广泛的方面，提供了一种主从模式，其允许透明时钟用作另一个时钟的主器件或从器件。
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.021 秒)